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參數(shù)資料
| 型號： | AN649 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | HFTA-04.0: Optical/Electrical Conversion in SDH/SONET Fiber Optic Systems |
| 中文描述： | HFTA - 04.0：光/電轉(zhuǎn)換/ SDH中的SONET光纖系統(tǒng) |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 247K |
| 代理商： | AN649 |
current. The PIN diode is relatively cheap and operates with the same supply voltage as the
electronic components, but for a given optical power it generates fewer electrons than the APD.
As a result, the APD provides a more sensitive receiver that can be placed farther away from
the transmitter. This advantage is offset by the need for an APD bias circuit, which (depending
on the APD type) must provide a reverse operating voltage in the 30V to 100V range.
Additionally, the APD adds more noise, costs more, and requires cooling.
The photodetector delivers the extracted current to a transimpedance amplifier (TIA), which
first converts the current to a voltage. This single-ended voltage is then amplified by the TIA
and (usually) converted to a differential signal as required by state-of-the-art receivers. The
TIA should provide both high overload tolerance and high input sensitivity (i.e., a large
dynamic range).
To provide the high input sensitivity necessary to receive optical signals weakened by
transmitter aging or long transmission distance (or both), the TIA noise must be reduced to a
minimum. On the other hand, a high overload tolerance is required to avoid bit errors due to
distortion in the presence of strong optical signals. Further, the TIA's maximum achievable gain
depends on the operating frequency. To ensure stable operation and the required bandwidth,
gain can be optimized only within a narrow range. This limitation may cause the output voltage
resulting from low-power optical signals to be insufficient for further processing. To amplify
small TIA voltages in the 1mV to 2mV range, the TIA function must be followed by a
postamplifier, which in most cases is a limiting amplifier (LA).
As the name implies, a limiting amplifier delivers a certain output-voltage swing whose
maximum is independent of the input signal strength. Also included is a loss-of-power indicator
(LOP) that warns when the incoming signal falls below a user-defined threshold. As a system-
dependent parameter, this threshold must be adjusted externally. A comparator with hysteresis
ensures chatter-free operation for the LOP flag when the signal is close to the threshold level.
A key component that follows the limiting amplifier in a receiver unit is the clock and data
recovery (CDR) circuit. The CDR performs timing and amplitude-level decisions on the
incoming signal, which leads to a time- and amplitude-regenerated data stream. First to be
recovered from the received signal is the clock. Several possibilities can support this clock-
recovery function (external SAW filter, external reference clock, etc.), but only the fully
integrated approach can save both cost and effort.
The challenge for an integrated clock-recovery circuit is to meet the jitter specification
recommended by the International Telecommunication Union-Telecom Standards Sector (ITU-
T). Jitter refers to the effect in which individual bit transitions ("0" to "1" and vice-versa) are
not exactly in phase. The effect becomes visual in an "eye diagram," in which several pseudo-
random bit-pattern sequences are superimposed. An eye diagram illustrates the quality of a data
stream in terms of the eye opening, measured using the "eye mask" (
Figure 2
).
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