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參數(shù)資料
| 型號(hào)： | AND8039 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | The One-Transistor Forward Converter |
| 中文描述： | 一個(gè)晶體管正激變換器 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 89K |
| 代理商： | AND8039 |
AND8039/D
http://onsemi.com
5
Design of the Primary Current Sensing Network
The UC3845, current–mode control IC is being used. Its
current sensing input has a maximum trip voltage of 1.0 volt
when the current–mode circuit is just starting–up. To
minimize the losses associated with the current sensing
resistance, one should use about a trip voltage of between 0.3
and 0.4 V. This results in a current sensing resistor of:
Rsc (R8)
VtripIpk(max)
0.3 2.24 A
0.13 ohms
make this value 0.1 ohms for a convenient off–the–shelf
value.
A spike filter should be placed between the current
sensing resistor (R8) and the IC. The time constant of this
R–C filter, if set too long, will enter a pulse–skipping mode
at light loads. If its time constant is made too short, then
some spikes may still enter the current comparator and
produce erratic pulsewidths. A time constant of 300 nS is a
good time.
One must first select one of the values. By making the R
larger, one can provide some series protection between the
power switch and the input pin of the IC. I will assign a value
of 1.0 K to R7. The capacitor then becomes:
C7
300 nS 1.0 K
300 pF
Design of the Bootstrap Start–Up Circuit
The purpose of this circuit is to initially start the control
circuit up from a turned–off state. The control circuit then
would draw its power directly from the transformer. The
most efficient circuit cuts off its start–up current after the
power supply has begun steady–state operation. This
reduces an unnecessary loss.
The circuit seen in the schematic (Figure 5) is essentially
a current–limited, high–voltage, linear regulator. When the
auxiliary power supply from the transformer is less than
10 V, the start–up circuit is operational. When the auxiliary
supply exceeds 10 V, it cuts off its collector current, which
is about 1.0 mA. A 10 uF or greater capacitor (C2) must be
placed on the auxiliary bus to store enough energy to
actually start the supply, since the IC will draw about 10 mA
in the operate mode.
R1 = (Vin(min)–Vz)/1.0 mA = (140–12)/1.0 mA
= 128 K Make 120 K
R2 = (Vin(min)–Vz)/2.0 mA
= 64 K Make 62 K
The zener diode (Z1) is a 500 mW 12 V, 1N5242
The selection of high voltage bipolar small signal
transistors is limited. An MPSW42 works nicely for Q1. The
purpose of D1 is to avoid stressing the base–emitter junction
in the reverse direction, if the auxiliary voltage goes far
above the +12 V base voltage. The typical reverse
breakdown voltage (V
(BR)EBO
) is between 3.0–6.0 V. A
1N4148 is going to be used for D1.
Design of the Voltage Feedback and Compensation
Design of the Resistor Divider
The UC3845 has a 2.5 volt reference. One should set the
value of the top resistor of the resistor divider (R11) between
2.0 k to 15 k ohms. This then makes the other values in the
compensation network reasonable values. This can be done
by selecting the sense current, that is the current allowed to
flow through the resistor divider. As an estimate one can first
calculate:
Isense
(28 V
2.5 V) 7.0 Kohms
3.65 mA
Using that sense current the lower resistor (R5) then
becomes:
R5
2.5 V 3.65 mA
closest resistance 680 ohms
684 ohms
The upper resistor is then:
R11
(28.0 V
or 6.98 kohms 1%
2.5 V) 3.65 mA)
6986 ohms
Design of the Feedback Loop Compensation
This is a current–mode controlled, forward converter
where only a 1–pole, 1–zero method of compensation is
required (2 poles if the op amp compensation is considered).
This provides maximum of +90 degrees phase boost, which
helps in avoiding unstable operation.
Determining the Control–to–Output Characteristic
The gain at DC for this topology is:
Vout)2VinVe(Nsec
13.5
ADC
(Vin
Npri)
GDC
20 Log (ADC)
22.6 dB
The output filter pole is:
ffp
1 (2 RLCo)
4.3 Hz (light load (0.5 A))
34.5 Hz (rated load (4.0 A))
where: R
L
is the equivalent resistance of the load
(V
out
/I
out
)
C
o
is the net value of the output capacitance
(C9+C10+C11)
The ESR zero of the net output capacitance is:
fz(esr)
1 (2 ResrCo)
1 (2 (50 m ohms) (660 F))
4822 Hz
where: R
esr
is all of the ESR resistances in parallel.
Calculating the Compensation Elements
Locating the compensating breakpoints:
fez
fep
ffp(light load)
fp(esr)
4.3 Hz
4.8 kHz
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