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參數(shù)資料
| 型號： | AP2010S |
| 廠商： | INTEGRATED CIRCUIT TECHNOLOGY CORP |
| 元件分類： | 模擬波形發(fā)生器 |
| 英文描述： | SINE, 0.1 MHz, WAVEFORM GENERATION, PDSO20 |
| 封裝： | LEAD FREE, SOP-20 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 246K |
| 代理商： | AP2010S |
AP2010
Sine-wave Generator for CCFL Supply
Anachip Corp.
www.anachip.com.tw
Rev.1.0 Oct. 28, 2005
7/9
Function Description (Continued)
Power Good
The power good flag (output terminal 16, PGOOD) is
high as long as the voltage at terminal 14 (DC) is
within 10% of the internal GAP voltage. The output
is an open collector NPN output. As there will be a
residual ripple voltage of twice the MWM frequency
at terminal 14 (DC) entering and leaving the PGOOD
mode is accompanied by several glitches. To
suppress them sufficiently the filter capacitor CF5 is
necessary. Be aware that if DIM control is active
also PGOOD is switching ON and OFF.
Solow Start
At start up the capacitor CS is at zero volts and held
there as long as the supply is below 4.2V.
Thereafter the capacitor is charged with 10uA until
it is up to 3V. As long as the output voltage of the
current loop amplifier intends to be higher than the
voltage at terminal 20 (SS) the output of the current
loop amplifier AMP is clamped to this voltage. By
this the duty cycle of the PWM controller is
increased slowly from zero to a value necessary to
generate the desired output current. This is to ramp
up the lamp voltage slowly until ignition at start up
time.
Current Limiting
This circuit compares the voltage drop (Vsd) at the
external PMOS during its on time with a voltage set
by the application. This reference voltage is the
voltage drop on the resistor between VCC and
terminal 8 (OCP). The voltage drop on this resistor
is due to an internal current sink of 200uA.
The
current sample is taken right in the center of the ON
time of the external PMOS transistor. If an
over-current is detected the drive of the external
power MOS transistors is switched off and Hiccup
Mode is entered. Because of IC internal restrictions
this measurement can only take place if the ON
time of the external PMOS is larger than 1.5us.
Hiccup Mode
If an over-current or an over-voltage is detected
then the external PMOS transistors is switched off
while the external NMOS is turned on. By this
setting the output voltage will decrease rapidly. At
the same time the external soft start capacitor at
terminal 20 (SS) is discharged by a current of 2uA.
As soon the voltage at it is below 0.8V a new soft
start is initiated. By this the pause between the
occurrence of an over-current and a restart is about
5 times the slow-start time.
Marking Information
( Top View )
SOP/SSOP-20
AP2010
YY WW ~
Logo
ID code
Year:"01" = 2001
"02" = 2002
Xth week: 01~52
~
Part Number
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