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參數(shù)資料
| 型號： | AP87C54 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 16 KBYTES USER PROGRAMMABLE EPROM |
| 中文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 290K |
| 代理商： | AP87C54 |
AUTOMOTIVE 87C54/87C54-20
PACKAGES
Part
Prefix
Package Type
87C54
87C54
AP
AN
40-Pin Plastic DIP
44-Pin PLCC
270849–2
DIP (PDIP)
270849–3
*
Do not connect reserved pins.
PAD (PLCC)
Figure 3. Pin Connections
PIN DESCRIPTIONS
V
CC
: Supply voltage.
V
SS
: Circuit ground.
V
SS1
: Secondary ground (in PLCC only). Provided to
reduce ground bounce and improve power supply
by-passing.
NOTE:
This pin is not a substitute for the V
SS
pin (pin 22).
Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1’s written to them
float, and in that state can be used as high-imped-
ance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong inter-
nal pullups when emitting1’s, and can source and
sink several LS TTL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are re-
quired during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(I
IL
, on the data sheet) because of the internal pull-
ups.
In addition, Port 1 serves the functions of the follow-
ing special features of the 87C54:
Port Pin
Alternate Function
P1.0
T2 (External Count Input to Timer/
Counter 2), Clock-Out
P1.1
T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
P1.2
ECI (External Count Input to the PCA)
P1.3
CEX0 (External I/O for Compare/
Capture Module 0)
P1.4
CEX1 (External I/O for Compare/
Capture Module 1)
P1.5
CEX2 (External I/O for Compare/
Capture Module 2)
P1.6
CEX3 (External I/O for Compare/
Capture Module 3)
P1.7
CEX4 (External I/O for Compare/
Capture Module 4)
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
(I
IL
, on the data sheet) because of the internal pull-
ups.
4
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