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參數(shù)資料
| 型號： | AP9467GM |
| 廠商： | ADVANCED POWER ELECTRONICS CORP |
| 元件分類： | JFETs |
| 英文描述： | 12 A, 40 V, 0.011 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | ROHS COMPLIANT, SOP-8 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 200K |
| 代理商： | AP9467GM |
4
2003 Semtech Corp.
www.semtech.com
PROTECTION PRODUCTS
SR12
Device Connection Options for Protection of Two
High-Speed Data Lines
The SR12 TVS is designed to protect two data lines from
transient over-voltages by clamping them to a fixed
reference. When the voltage on the protected line
exceeds the reference voltage (plus diode V
F) the steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
Data lines are connected at pins 2 and 3. The nega-
tive reference (REF1) is connected at pin 1. This pin
should be connected directly to a ground plane on the
board for best results. The path length is kept as short
as possible to minimize parasitic inductance.
The positive reference (REF2) is connected at pin 4.
The options for connecting the positive reference are
as follows:
1. To protect data lines and the power line, connect
pin 4 directly to the positive supply rail (V
CC). In this
configuration the data lines are referenced to the
supply voltage. The internal TVS diode prevents
over-voltage on the supply rail.
2. The SR12 can be isolated from the power supply by
adding a series resistor between pin 4 and V
CC. A
value of 10k
is recommended. The internal TVS
and steering diodes remain biased, providing the
advantage of lower capacitance.
3. In applications where no positive supply reference
is available, or complete supply isolation is desired,
the internal TVS may be used as the reference. In
this case, pin 4 is not connected. The steering
diodes will begin to conduct when the voltage on
the protected line exceeds the working voltage of
the TVS (plus one diode drop).
ESD Protection With RailClamps
RailClamps are optimized for ESD protection using the
rail-to-rail topology. Along with good board layout,
these devices virtually eliminate the disadvantages of
using discrete components to implement this topology.
Consider the situation shown in Figure 1 where dis-
crete diodes or diode arrays are configured for rail-to-
rail protection on a high speed line. During positive
duration ESD events, the top diode will be forward
biased when the voltage on the protected line exceeds
the reference voltage plus the V
F drop of the diode.
Data Line and Power Supply Protection Using Vcc as
reference
Data Line Protection with Bias and Power Supply
Isolation Resistor
Data Line Protection Using Internal TVS Diode as
Reference
Applications Information
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