ProASICPLUS Flash Family FPGAs v5.9 2-3 Clock Resources The Pro" />
參數資料
型號： APA1000-CGS624B
廠商： Microsemi SoC
文件頁數： 35/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 1M 624-CGA
標準包裝： 1
系列： ProASICPLUS
RAM 位總計： 202752
輸入/輸出數： 440
門數： 1000000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 通孔
封裝/外殼： 624-BCCGA
供應商設備封裝： 624-CCGA（32.5x32.5）
ProASICPLUS Flash Family FPGAs
v5.9
2-3
Clock Resources
The ProASICPLUS family offers powerful and flexible
control of circuit timing through the use of analog
circuitry. Each chip has two clock conditioning blocks
containing a phase-locked loop (PLL) core, delay lines,
phase shifter (0
° and 180°), clock multiplier/dividers, and
all
the
circuitry
needed
for
the
selection
and
interconnection of inputs to the global network (thus
providing bidirectional access to the PLL). This permits
the PLL block to drive inputs and/or outputs via the two
global lines on each side of the chip (four total lines).
This circuitry is discussed in more detail in the
Clock Trees
One of the main architectural benefits of ProASICPLUS is
the set of power- and delay-friendly global networks.
ProASICPLUS offers four global trees. Each of these trees
is based on a network of spines and ribs that reach all
the tiles in their regions (Figure 2-4 on page 2-4). This
flexible clock tree architecture allows users to map up to
88 different internal/external clocks in an APA1000
device. Details on the clock spines and various numbers
of the family are given in Table 2-1 on page 2-4.
The flexible use of the ProASICPLUS clock spine allows the
designer to cope with several design requirements. Users
implementing clock-resource intensive applications can
easily route external or gated internal clocks using global
routing spines. Users can also drastically reduce delay
penalties and save buffering resources by mapping
critical high fanout nets to spines. For design hints on
using these features, refer to Actel’s Efficient Use of
ProASIC Clock Trees application note.
Figure 2-3 High-Speed, Very Long-Line Resources
PAD RING
P
A
D
RING
I/O
RING
I/O
RING
High-Speed Very Long-Line Resouces
SRAM
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相關代理商/技術參數
參數描述
APA1000-CGS624M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 1M Gates 180MHz 0.22um Technology 2.5V 624-Pin CCGA 制造商:Microsemi Corporation 功能描述:APA1000-CGS624M - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA PROASIC+ 1M 624CCGA
APA1000-CQ208B 功能描述:IC FPGA PROASIC+ 1M 208-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:ProASICPLUS 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數:3411 邏輯元件/單元數:43661 RAM 位總計:2138112 輸入/輸出數:358 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27）
APA1000-CQ208M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 1M Gates 180MHz 0.22um Technology 2.5V 208-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 1M GATES 180MHZ 0.22UM 2.5V 208CQFP - Trays
APA1000-CQ352B 功能描述:IC FPGA PROASIC+ 1M 352-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:ProASICPLUS 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數:3411 邏輯元件/單元數:43661 RAM 位總計:2138112 輸入/輸出數:358 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27）
APA1000-CQ352M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 1M Gates 180MHz 0.22um Technology 2.5V 352-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 1M GATES 180MHZ 0.22UM 2.5V 352CQFP - Trays
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