ProASICPLUS Flash Family FPGAs 2- 62 v5.9 Asynchronous Write and Synchronous Rea" />
參數資料
型號: APA1000-LG624B
廠商: Microsemi SoC
文件頁數: 149/178頁
文件大小: 0K
描述: IC FPGA PROASIC+ 1M 624-LGA
標準包裝: 1
系列: ProASICPLUS
RAM 位總計: 202752
輸入/輸出數: 440
門數: 1000000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
封裝/外殼: 624-BCLGA
供應商設備封裝: 624-CLGA(32.5x32.5)
ProASICPLUS Flash Family FPGAs
2- 62
v5.9
Asynchronous Write and Synchronous Read to the Same Location
Note: *New data is read if WB
occurs before setup time. The stored data is read if WB occurs after hold time. The plot shows the
normal operation status.
Figure 2-35 Asynchronous Write and Synchronous Read to the Same Location
Table 2-59 TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
WBRCLKS
WB
↓ to RCLKS ↑ setup time
0.1
ns
WBRCLKH
WB
↓ to RCLKS ↑ hold time
7.0
ns
OCH
Old DO valid from RCLKS
3.0
ns
OCA/OCH
displayed
for
Access Timed Output
OCA
New DO valid from RCLKS
7.5
ns
DWRRCLKS
DI to RCLKS
↑ setup time
0
ns
DWRH
DI to WB
↑ hold time
1.5
ns
Notes:
1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.
2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write
signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be
read.
3. A setup or hold time violation will result in unknown output data.
WB = {WRB + WBLKB}
RCLKS
DO
t
BRCLKH
New Data*
Last Cycle Data
t
WRCKS
t
OCH
t
OCA
DI
t
DWRRCLK
t
DWRH
t
CCYC
t
CMH
t
CML
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