ProASICPLUS Flash Family FPGAs 2- 72 v5.9 FIFO Reset Notes: 1. During " />
參數(shù)資料
型號: APA1000-PQ208I
廠商: Microsemi SoC
文件頁數(shù): 160/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 1M 208-PQFP
標準包裝: 24
系列: ProASICPLUS
RAM 位總計: 202752
輸入/輸出數(shù): 158
門數(shù): 1000000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 208-BFQFP
供應商設(shè)備封裝: 208-PQFP(28x28)
ProASICPLUS Flash Family FPGAs
2- 72
v5.9
FIFO Reset
Notes:
1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) must be low.
2. The plot shows the normal operation status.
Figure 2-45 FIFO Reset
Table 2-68 TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CBRSH1
WCLKS or RCLKS
↑ hold from RESETB ↑
1.5
ns
Synchronous mode only
CBRSS1
WCLKS or RCLKS
↓ setup to RESETB ↑
1.5
ns
Synchronous mode only
ERSA
New EMPTY
↑ access from RESETB ↓
3.0
ns
FRSA
FULL
↓ access from RESETB ↓
3.0
ns
RSL
RESETB low phase
7.5
ns
THRSA
EQTH or GETH access from RESETB
4.5
ns
WBRSH1
WB
↓ hold from RESETB ↑
1.5
ns
Asynchronous mode only
WBRSS1
WB
↑ setup to RESETB ↑
1.5
ns
Asynchronous mode only
Note: During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low.
RESETB
EMPTY
EQTH, GETH
FULL
WRB/RBD1
Cycle Start
WCLKS, RCLKS1
tERSA, tFRSA
tTHRSA
tCBRSS
tWBRSS
tCBRSH
tWBRSH
tRSL
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