ProASICPLUS Flash Family FPGAs v5.9 2-11 The clock conditioning circuit can adva" />
參數(shù)資料
型號： APA1000-PQG208
廠商： Microsemi SoC
文件頁數(shù)： 93/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 1M 208-PQFP
標準包裝： 24
系列： ProASICPLUS
RAM 位總計： 202752
輸入/輸出數(shù)： 158
門數(shù)： 1000000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
ProASICPLUS Flash Family FPGAs
v5.9
2-11
The clock conditioning circuit can advance or delay the
clock up to 8 ns (in increments of 0.25 ns) relative to the
positive edge of the incoming reference clock. The system
also allows for the selection of output frequency clock
phases of 0° and 180°.
Prior to the application of signals to the rib drivers, they
pass through programmable delay units, one per global
network. These units permit the delaying of global
signals relative to other signals to assist in the control of
input set-up times. Not all possible combinations of input
and output modes can be used. The degrees of freedom
available in the bidirectional global pad system and in
the clock conditioning circuit have been restricted. This
avoids unnecessary and unwieldy design kit and software
work.
Notes:
1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments.
2. DLYA and DLYB are programmable delay lines, each with selectable values 0 ps, 250 ps, 500 ps, and 4 ns.
3. OBDIV will also divide the phase-shift since it takes place after the PLL Core.
Figure 2-11 PLL Block – Top-Level View and Detailed PLL Block Diagram
AVDD
AGND
GND
+
-
VDD
External Feedback Signal
GLA
GLB
Dynamic
Configuration Bits
Flash
Configuration Bits
8
27
4
Clock Conditioning
Circuitry
(Top level view)
Global MUX A OUT
Global MUX B OUT
See Figure 2-15
on page 2-15
Input Pins to the PLL
GLB
GLA
÷u
÷v
PLL Core
0°
180°
0
1
6
7
5
4
2
Delay Line 0.0 ns, 0.25 ns,
0.50 ns and 4.00 ns
P+
P-
Clock from Core
(GLINT mode)
CLK
1
0
Deskew
Delay
2.95 ns
1
2
3
Delay Line
0.25 ns to
4.00 ns,
16 steps,
0.25 ns
increments
3
1
2
Delay Line 0.0 ns, 0.25 ns,
0.50 ns and 4.00 ns
Clock from Core
(GLINT mode)
CLKA
EXTFB
XDLYSEL
Bypass Secondary
Bypass Primary
FIVDIV[4:0]
FBDIV[5:0]
FBSEL[1:0]
OAMUX[1:0]
DLYA[1:0]
DLYB[1:0]
OBDIV[1:0]
OBMUX[2:0]
OADIV[1:0]
FBDLY[3:0]
÷n
÷m
Clock Conditioning Circuitry Detailed Block Diagram
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
APA1000-PQG208A 功能描述:IC FPGA PROASIC+ 1M 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
APA1000-PQG208I 功能描述:IC FPGA PROASIC+ 1M 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
APA1000-PQG208M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 1M Gates 180MHz 0.22um Technology 2.5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 1M GATES 180MHZ 0.22UM 2.5V 208PQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA PROASIC+ 1M 208PQFP
APA1000-PQGB 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA1000-PQGES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
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