ProASICPLUS Flash Family FPGAs v5.9 2-41 Table 2-26 AC Specifications (3" />
參數(shù)資料
型號: APA150-TQG100A
廠商: Microsemi SoC
文件頁數(shù): 126/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 150K 100-TQFP
標準包裝: 90
系列: ProASICPLUS
RAM 位總計: 36864
輸入/輸出數(shù): 66
門數(shù): 150000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 100-LQFP
供應商設備封裝: 100-TQFP(14x14)
ProASICPLUS Flash Family FPGAs
v5.9
2-41
Table 2-26 AC Specifications (3.3 V PCI Revision 2.2 Operation)
Symbol Parameter
Condition
Commercial/Industrial/Military/MIL-STD- 883
Units
Min.
Max.
IOH(AC)
Switching Current High
0 < VOUT ≤ 0.3VDDP
*
–12VDDP
mA
0.3VDDP ≤ VOUT < 0.9VDDP
*
(–17.1 + (VDDP – VOUT))
mA
0.7VDDP < VOUT < VDDP
*
See equation C – page 124 of
the PCI Specification
document rev. 2.2
(Test Point)
VOUT = 0.7VDDP
*
–32VDDP
mA
IOL(AC)
Switching Current Low
VDDP > VOUT ≥ 0.6VDDP
*
16VDDP
mA
0.6VDDP > VOUT > 0.1VDDP
1
(26.7VOUT)mA
0.18VDDP > VOUT > 0
*
See equation D – page 124 of
the PCI Specification
document rev. 2.2
(Test Point)
VOUT = 0.18VDDP
38VDDP
mA
ICL
Low Clamp Current
–3 < VIN ≤ –1
–25 + (VIN + 1)/0.015
mA
ICH
High Clamp Current
VDDP + 4 > VIN ≥ VDDP + 1
25 + (VIN – VDDP – 1)/0.015
mA
slewR
Output Rise Slew Rate
0.2VDDP to 0.6VDDP load
*
14
V/ns
slewF
Output Fall Slew Rate
0.6VDDP to 0.2VDDP load
*
14
V/ns
Note: * Refer to the PCI Specification document rev. 2.2.
Pin
Output
Buffer
1/2 in. maxx
10 pF
1k
Ω
Pin
Output
Buffer
10 pF
1k
Ω
Pad Loading Applicable to the Rising Edge PCI
Pad Loading Applicable to the Falling Edge PCI
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