ProASICPLUS Flash Family FPGAs 2- 60 v5.9 Synchronous SRAM Write Note: The pl" />
參數(shù)資料
型號: APA450-FGG484I
廠商: Microsemi SoC
文件頁數(shù): 147/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 450K 484-FBGA
標準包裝: 40
系列: ProASICPLUS
RAM 位總計: 110592
輸入/輸出數(shù): 344
門數(shù): 450000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 484-BGA
供應商設備封裝: 484-FPBGA(23x23)
ProASICPLUS Flash Family FPGAs
2- 60
v5.9
Synchronous SRAM Write
Note: The plot shows the normal operation status.
Figure 2-33 Synchronous SRAM Write
Table 2-57 TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
DCH
DI hold from WCLKS
0.5
ns
DCS
DI setup to WCLKS
1.0
ns
WACH
WADDR hold from WCLKS
0.5
ns
WDCS
WADDR setup to WCLKS
1.0
ns
WPCA
New WPE access from WCLKS
3.0
ns
WPE is invalid while
PARGEN is active
WPCH
Old WPE valid from WCLKS
0.5
ns
WRCH, WBCH WRB & WBLKB hold from WCLKS
0.5
ns
WRCS, WBCS
WRB & WBLKB setup to WCLKS
1.0
ns
Note: On simultaneous read and write accesses to the same location, DI is output to DO.
WCLKS
WPE
WADDR, DI
WRB, WBLKB
Cycle Start
tWRCH, tWBCH
tWRCS, tWBCS
tDCS, tWDCS
tWPCH
tDCH, tWACH
tWPCA
tCMH
tCML
tCCYC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
APA450-FGG484I-MOT 制造商:Microsemi Corporation 功能描述:
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