ProASICPLUS Flash Family FPGAs v5.9 2-65 Asynchronous FIFO Full and Empty Transi" />
參數(shù)資料
型號(hào)： APA600-FG484I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 152/178頁(yè)
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 600K 484-FBGA
標(biāo)準(zhǔn)包裝： 40
系列： ProASICPLUS
RAM 位總計(jì)： 129024
輸入/輸出數(shù)： 370
門(mén)數(shù)： 600000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
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ProASICPLUS Flash Family FPGAs
v5.9
2-65
Asynchronous FIFO Full and Empty Transitions
The asynchronous FIFO accepts writes and reads while
not full or not empty. When the FIFO is full, all writes are
inhibited. Conversely, when the FIFO is empty, all reads
are inhibited. A problem is created if the FIFO is written
to during the transition from full to not full, or read
during the transition from empty to not empty. The
exact time at which the write or read operation changes
from inhibited to accepted after the read (write) signal
which causes the transition from full or empty to not full
or not empty is indeterminate. For slow cycles, this
indeterminate period starts 1 ns after the RB (WB)
transition, which deactivates full or not empty and ends
3 ns after the RB (WB) transition. For fast cycles, the
indeterminate period ends 3 ns (7.5 ns – RDL (WRL)) after
the RB (WB) transition, whichever is later (Table 2-1 on
The timing diagram for write is shown in Figure 2-35 on
page 2-62. The timing diagram for read is shown in
Figure 2-36 on page 2-63. For basic SRAM configurations,
see Table 2-14 on page 2-22. When reset is asserted, the
empty flag will be asserted, the counters will reset, the
outputs go to zero, but the internal RAM is not erased.
Enclosed Timing Diagrams – FIFO Mode:
The following timing diagrams apply only to single cell;
they are not applicable to cascaded cells. For more
information, refer to the ProASICPLUS RAM/FIFO Blocks
application note.
Table 2-62 Memory Block FIFO Interface Signals
FIFO Signal
Bits
In/Out
Description
WCLKS
1
In
Write clock used for synchronization on write side
RCLKS
1
In
Read clock used for synchronization on read side
LEVEL [0:7]*
8
In
Direct configuration implements static flag logic
RBLKB
1
In
Read block select (active Low)
RDB
1
In
Read pulse (active Low)
RESET
1
In
Reset for FIFO pointers (active Low)
WBLKB
1
In
Write block select (active Low)
DI[0:8]
9
In
Input data bits [0:8], [8] will be generated if PARGEN is true
WRB
1
In
Write pulse (active Low)
FULL, EMPTY
2
Out
FIFO flags. FULL prevents write and EMPTY prevents read
EQTH, GEQTH*
2
Out
EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.
GEQTH is true when the FIFO holds (LEVEL) words or more
DO[0:8]
9
Out
Output data bits [0:8]
RPE
1
Out
Read parity error (active High)
WPE
1
Out
Write parity error (active High)
LGDEP [0:2]
3
In
Configures DEPTH of the FIFO to 2 (LGDEP+1)
PARODD
1
In
Selects Odd parity generation/detect when high, Even when low
Note: *LEVEL is always eight bits (0000.0000, 0000.0001). That means for values of DEPTH greater than 256, not all values will be
possible, e.g. for DEPTH = 512, the LEVEL can only have the values 2, 4, . . ., 512. The LEVEL signal circuit will generate signals that
indicate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL.
Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs.
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