ProASICPLUS Flash Family FPGAs 2- 56 v5.9 Synchronous SRAM Read, Pipeline Mode O" />
參數(shù)資料
型號: APA600-FGG676
廠商: Microsemi SoC
文件頁數(shù): 142/178頁
文件大小: 0K
描述: IC FPGA PROASIC+ 600K 676-FBGA
標準包裝: 40
系列: ProASICPLUS
RAM 位總計: 129024
輸入/輸出數(shù): 454
門數(shù): 600000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
ProASICPLUS Flash Family FPGAs
2- 56
v5.9
Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Note: The plot shows the normal operation status.
Figure 2-29 Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 2-53 TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = 0°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
OCA
New DO access from RCLKS
2.0
ns
OCH
Old DO valid from RCLKS
0.75
ns
RACH
RADDR hold from RCLKS
0.5
ns
RACS
RADDR setup to RCLKS
1.0
ns
RDCH
RDB hold from RCLKS
0.5
ns
RDCS
RDB setup to RCLKS
1.0
ns
RPCA
New RPE access from RCLKS
4.0
ns
RPCH
Old RPE valid from RCLKS
1.0
ns
RCLKS
RPE
DO
New Valid Data Out
Cycle Start
New RPE Out
RADDR
New Valid
Address
RDB, RBLKB
tRACS
tOCA
tRPCH
tOCH
tRPCA
tCML
tCMH
tCCYC
tRACH
tRDCH
tRDCS
Old Data Out
Old RPE Out
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參數(shù)描述
APA600-FGG676I 功能描述:IC FPGA PROASIC+ 600K 676-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:ProASICPLUS 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP,帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP(75x75)
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