ProASICPLUS Flash Family FPGAs v5.9 2-29 Logic-Tile Contributio" /> 
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    參數(shù)資料
    

    


    


    
型號：
APA600-PQG208I

    

    
廠商：
Microsemi SoC

    

    
文件頁數(shù)：
112/178頁

    

    
文件大小：
0K

    

    
描述：
IC FPGA PROASIC+ 600K 208-PQFP

    

    
標準包裝：
24

    

    
系列：
ProASICPLUS

    

    
RAM 位總計：
129024
    		

    

    
輸入/輸出數(shù)：
158
    		

    

    
門數(shù)：
600000
    		

    

    
電源電壓：
2.3 V ~ 2.7 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
-40°C ~ 85°C
    		

    

    
封裝/外殼：
208-BFQFP
    		

    

    
供應商設備封裝：
208-PQFP（28x28）
    		

    

    

    

	
    
    
    

    
    
	
    ProASICPLUS Flash Family FPGAs
    v5.9
    2-29
    Logic-Tile Contribution—Plogic
    Plogic, the logic-tile component of AC power dissipation, is given by
    Plogic = P3 * mc * Fs
    where:
    I/O Output Buffer Contribution—Poutputs
    Poutputs, the I/O component of AC power dissipation, is given by
    Poutputs = (P4 + (Cload * VDDP
    2)) * p * Fp
    where:
    I/O Input Buffer's Buffer Contribution—Pinputs
    The input’s component of AC power dissipation is given by
    Pinputs = P8 * q * Fq
    where:
    PLL Contribution—Ppll
    Ppll = P9 * Npll
    where:
    RAM Contribution—Pmemory
    Finally, Pmemory, the memory component of AC power consumption, is given by
    Pmemory = P6 * Nmemory * Fmemory * Ememory
    where:
    P3
    =
    1.4
    μW/MHz is the average power consumption of a logic tile per MHz of its output toggling rate. The
    maximum output toggling rate is Fs/2.
    mc
    =
    the number of logic tiles switching during each Fs cycle
    Fs
    =
    the clock frequency
    P4
    =
    326
    μW/MHz is the intrinsic power consumption of an output pad normalized per MHz of the output
    frequency. This is the total I/O current VDDP.
    Cload =
    the output load
    p
    =
    the number of outputs
    Fp
    =
    the average output frequency
    P8
    =
    29
    μW/MHz is the intrinsic power consumption of an input pad normalized per MHz of the input
    frequency.
    q
    =
    the number of inputs
    Fq
    =
    the average input frequency
    P9
    =
    7.5 mW. This value has been estimated at maximum PLL clock frequency.
    NPll
    =
    number of PLLs used
    P6
    =
    175 W/MHz is the average power consumption of a memory block per MHz of the clock
    Nmemory
    =
    the number of RAM/FIFO blocks
    (1 block = 256 words * 9 bits)
    Fmemory
    =
    the clock frequency of the memory
    Ememory
    =
    the average number of active blocks divided by the total number of blocks (N) of the memory.
    Typical values for Ememory would be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8,
    9, 16, and 32 memory configuration
    In addition, an application-dependent component to Ememory can be considered. For
    example, for a 1kx8 memory configuration using only 1 cycle out of 2, Ememory = 1/4*1/2 = 1/8
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
APA600-PQG208M
 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um Technology 2.5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 600K GATES 180MHZ 0.22UM 2.5V 208PQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 158 I/O 208PQFP 制造商:Microsemi Corporation 功能描述:IC FPGA PROASIC+ 600K 208PQFP

    

    
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 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs

    

    
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