ProASICPLUS Flash Family FPGAs v5.9 2-1 General Description Routing Resources
參數(shù)資料
型號： APA750-FGG896I
廠商： Microsemi SoC
文件頁數(shù)： 13/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 750K 896-FBGA
標準包裝： 27
系列： ProASICPLUS
RAM 位總計： 147456
輸入/輸出數(shù)： 562
門數(shù)： 750000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 896-BGA
供應商設備封裝： 896-FBGA（31x31）
ProASICPLUS Flash Family FPGAs
v5.9
2-1
General Description
Routing Resources
The routing structure of ProASICPLUS devices is designed
to provide high performance through a flexible four-
level hierarchy of routing resources: ultra-fast local
resources, efficient long-line resources, high-speed, very
long-line
resources,
and
high
performance
global
networks.
The ultra-fast local resources are dedicated lines that
allow the output of each tile to connect directly to every
input of the eight surrounding tiles (Figure 2-1).
The efficient long-line resources provide routing for
longer distances and higher fanout connections. These
resources vary in length (spanning 1, 2, or 4 tiles), run
both vertically and horizontally, and cover the entire
ProASICPLUS device (Figure 2-2 on page 2-2). Each tile can
drive signals onto the efficient long-line resources, which
can in turn access every input of every tile. Active buffers
are inserted automatically by routing software to limit
the loading effects due to distance and fanout.
The high-speed, very long-line resources, which span the
entire device with minimal delay, are used to route very
long or very high fanout nets. (Figure 2-3 on page 2-3).
The high-performance global networks are low-skew,
high fanout nets that are accessible from external pins or
from internal logic (Figure 2-4 on page 2-4). These nets
are typically used to distribute clocks, resets, and other
high fanout nets requiring a minimum skew. The global
networks are implemented as clock trees, and signals can
be introduced at any junction. These can be employed
hierarchically with signals accessing every input on all
tiles.
Figure 2-1 Ultra-Fast Local Resources
L
Inputs
Output
Ultra-Fast
Local Lines
(connects a tile to the
adjacent tile, I/O buffer,
or memory block)
L
LL
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
APA750-FGGB 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA750-FGGES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA750-FGGI 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA750-FGGM 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA750-FGGPP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
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