ProASICPLUS Flash Family FPGAs v5.9 2-19 PLL I/O Constraints PLL locking is guar" />
參數(shù)資料
型號: APA750-PQG208I
廠商: Microsemi SoC
文件頁數(shù): 101/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 750K 208-PQFP
標準包裝: 24
系列: ProASICPLUS
RAM 位總計: 147456
輸入/輸出數(shù): 158
門數(shù): 750000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 208-BFQFP
供應商設(shè)備封裝: 208-PQFP(28x28)
ProASICPLUS Flash Family FPGAs
v5.9
2-19
PLL I/O Constraints
PLL locking is guaranteed only when the following constraints are followed:
Table 2-10 PLL I/O Constraints
TJ –40°C
Value TJ > –40°C
I/O Type
PLL locking is guaranteed only when using low drive strength and
low slew rate I/O. PLL locking may be inconsistent when using high
drive strength or high slew rate I/Os
No Constraints
SSO
APA300
Hermetic packages
8 SSO
With FIN
180 MHz and
outputs
switching
simultaneously
Plastic packages
16 SSO
APA600
Hermetic packages
16 SSO
Plastic packages
32 SSO
APA1000
Hermetic packages
16 SSO
Plastic packages
32 SSO
APA300
Hermetic packages
12 SSO
With FIN
50 MHz and half
outputs switching on positive
clock edge, half switching on
the negative clock edge no less
than 10 ns later
Plastic packages
20 SSO
APA600
Hermetic packages
32 SSO
Plastic packages
64 SSO
APA1000
Hermetic packages
32 SSO
Plastic packages
64 SSO
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