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參數(shù)資料
| 型號(hào)： | APV1-FREQ-L-S-P1-T |
| 廠商： | ABRACON CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 38 MHz - 640 MHz, PECL OUTPUT |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 750K |
| 代理商： | APV1-FREQ-L-S-P1-T |
Frequency Range
Operating Temperature
Storage Temperature
Overall Frequency Stability
Supply Voltage (Vdd)
Phase Jitter RMS (12KHz-20MHz)
Period Jitter (peak to peak)
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
|||||||||||||||
APV SERIES
STANDARD SPECIFICATIONS:
APPLICATIONS:
SONET, Fiber Channel, SERDES
HDTV, OBSAI, CPRI, PCI Express, 1394
FEATURES:
Low Jitter
CMOS, PECL or LVDS Output
Low Power ( 2.5, 3.3V )
Sub 1pS ( 12kHz - 20MHz )
re
v3.1-8/06
PARAMETERS
PECL
38 MHz to 640 MHz
0°C to + 70°C (see options)
-55°C to +125°C
± 50 ppm max. (see options)
2.25V to 3.63V (2.5V to 3.3V ± 10%)
0.5pS Typ, 1pS Max
20pS typ., 30pS max up to 320 MHz; 50pS typ., 70pS max 321MHz to 640MHz
Tri-State Function
For CMOS and LVDS = "1" (VIH 0.7* Vdd) or open: Oscillation;
"0" (VIL < 0.3* Vdd): No oscillation/Hi Z
For PECL See TriState Pin Operation table P Option Standard PECL OE
"0" (VIL < 0.3* Vdd): or Open: Oscillation; "1" (VIH 0.7* Vdd): No oscillation/Hi Z
P Option = "1" (VIH 0.7* Vdd) or open: Oscillation;
"0" (VIL < 0.3* Vdd): No oscillation/Hi Z
5.0 x 7.0 x 1.8mm
Supply Current (IDD)
Symmetry (Duty Cycle)
Output Logic High
Output Logic Low
Rise time
Fall time
45% min, 50% typical, 55% max.
VDD -1.025V min, VDD -0.880V max.
VDD -1.810V min, VDD -1.620V max.
1.5ns max, 0.6nSec typical
LVDS
Supply Current (IDD)
Output Clock Duty Cycle @ 1.25V
Output Differential Voltage (VOD)
VDD Magnitude Change (
VOD)
Output High Voltage
Output Low Voltage
Offset Voltage [RL = 100
]
Offset Magnitude Voltage[RL = 100
]
Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V]
Differential Clock Rise Time (tr) [RL=100
, CL=10pF]
Differential Clock Fall Time (tf) [RL=100
, CL=10pF]
CMOS
Supply Current
Symmetry (Duty Cycle)
Rise/ Fall Time
30mA max (38MHz<Fo<320MHz)
45% min, 50% typ, 55% max,
45% min, 50% typical, 55% max
247mV min, 355mV typical, 454mV max
-50mV min, 50mV max
VOH = 1.6V max, 1.4V typical
VOL = 0.9V min, 1.1V typical
VOS = 1.125V min, 1.2V typical, 1.375V max
VOS = 0mV min, 3mV typical, 25mV max
±10
A max, ±1A typical
0.7ns typical, 1.0ns max, 0.2nS min
: PRELIMINARY
45mA max(for 38MHz<Fo<320MHz), 70mA max (320MHz<Fo<640MHz)
65mA max (for 38MHz<Fo<320MHz), 90mA max (320MHz<Fo<640MHz)
(0.3V ~ 3.0V w/15 pF load) 0.7nS Typ.; (20%-80% w/50 Load) 0.3nS Typ.
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