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參數(shù)資料
| 型號(hào)： | ARM610 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元）) |
| 中文描述： | 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲(chǔ)器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元）） |
| 文件頁(yè)數(shù)： | 53/174頁(yè) |
| 文件大?。?/td> | 694K |
| 代理商： | ARM610 |
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Instruction Set - LDR, STR
ARM610 Data Sheet
4-25
O
4.7.1 Offsets and auto-indexing
The offset from the base may be either a 12-bit unsigned binary immediate value in
the instruction, or a second register (possibly shifted in some way). The offset may be
added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification
may be performed either before (pre-indexed, P=1) or after (post-indexed, P=0) the
base is used as the transfer address.
The W bit gives optional auto increment and decrement addressing modes. The
modified base value may be written back into the base (W=1), or the old base value
may be kept (W=0). In the case of post-indexed addressing, the write back bit is
redundant and is always set to zero, since the old base value can be retained by setting
the offset to zero. Therefore post-indexed data transfers always write back the modified
base. The only use of the W bit in a post-indexed data transfer is in privileged mode
code, where setting the W bit forces non-privileged mode for the transfer, allowing the
operating system to generate a user address in a system where the memory
management hardware makes suitable use of this hardware.
4.7.2 Shifted register offset
The 8 shift control bits are described in the data processing instructions section.
However, the register specified shift amounts are not available in this instruction class.
See
·
4.4.2 Shiftson page 4-11.
4.7.3 Bytes and words
This instruction class may be used to transfer a byte (B=1) or a word (B=0) between
an ARM610 register and memory.
The action of LDR(B) and STR(B) instructions is influenced by the
BIGEND
control
signal. The two possible configurations are described below.
Little-endian configuration
A byte load (LDRB) expects the data on data bus inputs 7 through 0 if the supplied
address is on a word boundary, on data bus inputs 15 through 8 if it is a word address
plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the
destination register, and the remaining bits of the register are filled with zeros. Please
see
·
Figure 3-2: Little endian addresses of bytes within wordson page 3-3.
A byte store (STRB) repeats the bottom 8 bits of the source register four times across
data bus outputs 31 through 0. The external memory system should activate the
appropriate byte subsystem to store the data.
A word load (LDR) will normally use a word aligned address. However, an address
offset from a word boundary will cause the data to be rotated into the register so that
the addressed byte occupies bits 0 to 7. This means that halfwords accessed at offsets
0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the
register. Two shift operations are then required to clear or to sign extend the upper 16
bits. This is illustrated in
·
Figure 4-13: Little-endian offset addressingon page 4-26.
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