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參數(shù)資料
| 型號： | AS3842 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Current Mode Controller |
| 中文描述： | 電流模式控制器 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 155K |
| 代理商： | AS3842 |
15
ASTEC Semiconductor
In most typical power supply designs, the con-
verters output voltage is divided down and moni-
tored at the error amplifiers inverting input, V
FB
. A
simple resistor divider network is used and is
scaled such that the voltage at V
FB
is 2.5 V when
the converters output is at the desired voltage.
The voltage at V
FB
is then compared to the inter-
nal 2.5 V reference and any slight difference is
amplified by the high gain of the error amplifier.
The resulting error amplifier output is level shifted
by two diode drops and is then divided by three to
provide a 0 to 1 V reference (V
E
) to one input of
the current sense comparator. The level shifting
reduces the input voltage range of the current
sense input and prevents the output from going
high when the error amplifier output is forced to its
low state. An internal clamp limits V
E
to 1.0 V. The
purpose of the clamp is discussed in Section 1.5.
1.4.1 Loop compensation
Loop compensation of a power supply is neces-
sary to ensure stability and provide good line/load
regulation and dynamic response. It is normally
provided by a compensation network connected
between the error amplifiers output (COMP) and
inverting input as shown in Figure 17. The type of
network used depends on the converter topology
and in particular, the characteristics of the major
functional blocks within the supply i.e. the error
amplifier, the modulator/switching circuit, and the
output filter. In general, the network is designed
such that the converters overall gain/phase
response approaches that of a single pole with a
D20 dB/decade rolloff, crossing unity gain at the
highest possible frequency (up to f
SW
/4) for good
dynamic response, with adequate phase margin
(> 45) to ensure stability.
Figure 18 shows the Gain/Phase response of the
error amplifier. The unity gain crossing is at
1.2 MHz with approximately 57C of phase mar-
gin. This information is useful in determining the
configuration and characteristics required for the
compensation network.
One of the simplest types of compensation net-
works is shown in Figure 19. An RC network pro-
vides a single pole which is normally set to
compensate for the zero introduced by the output
capacitors ESR. The frequency of the pole (f
P
) is
determined by the formula;
(5)
AS384x
Current Mode Controller
10
1
10
2
10
3
10
4
10
5
10
6
10
7
–20
0
20
40
60
80
240
210
180
150
120
90
60
30
0
–30
–60
Frequency (Hz)
Gain
Phase
P
G
V
OUT
R
I
R
BIAS
2.50 V
To PWM
C
F
R
F
+
D
E/A
Figure 18. Gain/Phase Response of the AS3842
Figure 19. A Typical Compensation Network
P
=
1
2
π
R
C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS3843 | Current Mode Controller |
| AS3843D1413 | Current Mode Controller |
| AS3843D14T | Current Mode Controller |
| AS3843D813 | Current Mode Controller |
| AS3843D8T | Current Mode Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS3842D1413 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current Mode Controller |
| AS3842D14T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current Mode Controller |
| AS3842D813 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current Mode Controller |
| AS3842D8T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current Mode Controller |
| AS3842N13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current Mode Controller |
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