參數(shù)資料
型號: AS3844D1413
廠商: Electronic Theatre Controls, Inc.
英文描述: Current Mode Controller
中文描述: 電流模式控制器
文件頁數(shù): 16/20頁
文件大小: 155K
代理商: AS3844D1413
16
ASTEC Semiconductor
Resistors R
1
and R
F
set the low frequency gain
and should be chosen to provide the highest pos-
sible gain, without exceeding the unity gain cross-
ing frequency limit of f
SW
/4. R
BIAS
, in conjunction
with R
1
, sets the converters output voltage; but
has no effect on the loop gain/phase response.
There are a few converter design considerations
associated with the error amplifier. First, the val-
ues of the divider network (R
1
and R
BIAS
) should
be kept low in order to minimize errors caused by
the error amplifiers input bias current. An output
voltage error equal to the product of the input
bias current and the equivalent divider resis-
tance, can be quite significant with divider values
greater than 5 k. Low divider resistor values
also help to improve the noise immunity of the
sensitive V
FB
input.
The second consideration is that the error ampli-
fier will typically source only 0.8 mA; thus, the
value of feedback resistance (R
F
) should be no
lower than 5 k in order to maintain the error
amplifiers full output range. In practice, however,
the feedback resistance required is usually much
greater than 5 k, hence this limitation is nor-
mally not a problem.
Some power supply topologies may require a
more elaborate compensation network. For
example, flyback and boost converters operating
with continuous current have transfer functions
that include a right half plane (RHP) zero. These
types of systems require an additional pole ele-
ment within the compensation network. A
detailed discussion of loop compensation, how-
ever, is beyond the scope of this application note.
1.5 I
SENSE
current comparator/PWM
latch
The current sense comparator (sometimes
called the PWM comparator) and accompanying
latch circuitry make up the pulse width modula-
tor (PWM). It provides pulse-by-pulse current
sensing/limiting and generates a variable duty
ratio pulse train which controls the output voltage
of the power supply. Included is a high speed
comparator followed by ECL type logic circuitry
which has very low propagation delays and
switching noise. This is essential for high fre-
quency power supply designs. The comparator
has been designed to provide guaranteed perfor-
mance with the current sense input below ground.
The PWM latch ensures that only one pulse is
allowed at the output for each oscillator period.
The inverting input to the current sense com-
parator is internally connected to the level shifted
output of the error amplifier (V
E
) as discused in
the previous section. The non-inverting input is
the I
SENSE
input (pin 3). It monitors the switched
inductor current of the converter.
Figure 20 shows the current sense/PWM circuitry
of the AS3842, and associated waveforms. The
output is set high by an internal clock pulse and
remains high until one of two conditions occurs;
1) the oscillator times out (Section 1.3) or 2) the
PWM latch is set by the current sense compara-
tor. During the time when the output is high, the
converters switching device is turned on and
current flows through resistor R
S
. This produces
a stepped ramp waveform at pin 3 as shown in
Figure 20. The current will continue to ramp up
until it reaches the level of V
E
at the inverting
input. At that point, the comparators output goes
high, setting the PWM latch and the output pulse
is then terminated. Thus, V
E
is a variable refer-
ence for the current sense comparator, and it
controls the peak current sensed by R
S
on a
cycle-by-cycle basis. V
S
varies in proportion to
changes in the input voltage/current (inner con-
trol loop) while V
E
varies in proportion to changes
in the converters output voltage/current (outer
control loop). The two control loops merge at the
current sense comparator, producing a variable
duty ratio pulse train that controls the output of
the converter.
AS384x
Current Mode Controller
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