參數(shù)資料
型號(hào): AS4LC1M16E5-50TI
廠商: Electronic Theatre Controls, Inc.
英文描述: 3V 1M X 6 CMOS DRAM (EDO)
中文描述: 3V的100萬× 6的CMOS的DRAM(江戶)
文件頁數(shù): 4/22頁
文件大?。?/td> 604K
代理商: AS4LC1M16E5-50TI
AS4LC1M16E5
4/11/01
Alliance Semiconductor
4
DC electrical characteristics
Shaded areas indicate advance information.
Parameter
Symbol
Test conditions
0V
V
in
V
CC
(max)
Pins not under test = 0V
D
OUT
disabled, 0V
V
out
V
CC
(max)
RAS, UCAS, LCAS, Address cycling;
t
RC
=min
RAS = UCAS = LCAS
V
IH
,
all other inputs at V
IH
or V
IL
-50
-60
Unit
Notes
Min
Max
Min
Max
Input leakag
e c
urrent
I
IL
-2
+2
-2
+2
μ
A
Output leakage current
I
OL
-2
+2
-2
+2
μ
A
Operating power
supply current
I
CC1
140
130
mA
4,5
TTL standby power
supply current
I
CC2
2.0
2.0
mA
Average power supply
current, RAS refresh
mode or CBR
I
CC3
RAS cycling, UCAS = LCAS
V
IH
,
t
RC
= min of RAS low after XCAS low.
80
70
mA
4
EDO page mode average
power supply current
I
CC4
RAS = V
IL
, UCAS or LCAS,
address cycling: t
HPC
= min
RAS = UCAS = LCAS = V
CC
- 0.2V
F = 0
85
75
mA
4, 5
CMOS standby power
supply current
I
CC5
1
1
mA
Output voltage
V
OH
V
OL
I
OUT
= -5.0 mA
I
OUT
= 4.2 mA
2.4
2.4
V
0.4
0.4
V
CAS before RAS refresh
current
I
CC6
RAS, UCAS or LCAS cycling, t
RC
= min
80
70
mA
Self refresh current
I
CC7
RAS = UCAS = LCAS
0.2V,
WE = OE
V
CC
- 0.2V,
all other inputs at 0.2V or
V
CC
- 0.2V
0.5
0.5
mA
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PDF描述
AS4LC1M16E5-60JC 3V 1M X 6 CMOS DRAM (EDO)
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