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March 2001
Copyright Alliance Semiconductor. All rights reserved.
AS4LC4M4E0
AS4LC4M4E1
4Mx4 CMOS DRAM (EDO) Family
4/11/01; V1.1
Alliance Semiconductor
P. 1 of 15
Features
Organization: 4,194,304 words × 4 bits
High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
Low power consumption
- Active: 500 mW max
- Standby:3.6 mW max, CMOS I/O
Extended data out
Refresh
- 4096 refresh cycles, 64 ms refresh interval for AS4LC4M4E0
- 2048 refresh cycles, 32 ms refresh interval for AS4LC4M4E1
- RAS-only or CAS-before-RAS refresh or self-refresh
TTL-compatible, three-state I/O
JEDEC standard package
- 300 mil, 24/26-pin SOJ
3V power supply
Industrial and commercial temperature available
Pin arrangement
A8
A7
A6
A5
A4
GND
A10
A0
A1
A2
A3
V
CC
GND
I/O3
I/O2
CAS
OE
A9
V
CC
I/O0
I/O1
WE
RAS
1
2
3
4
5
6
24
23
22
21
20
19
*NC/A11
7
8
9
10
11
12
18
17
16
15
14
13
SOJ
A
A8
A7
A6
A5
A4
GND
A10
A0
A1
A2
A3
V
CC
GND
I/O3
I/O2
CAS
OE
A9
V
CC
I/O0
I/O1
WE
RAS
1
2
3
4
5
6
24
23
22
21
20
19
*NC/A11
7
8
9
10
11
12
18
17
16
15
14
13
TSOP
A
* NC on 2K refresh version; A11 on 4K refresh version
Pin(s)
Description
A0 to A11
Address inputs
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
I/O0 to I/O3
Input/output
OE
Output enable
V
CC
GND
Power
Ground
Selection guide
Symbol
AS4LC4M4E0/E1-50 AS4LC4M4E0/E1-60 Unit
Maximum
RAS
access time
t
RAC
t
CAA
t
CAC
t
OEA
t
RC
t
PC
I
CC1
I
CC5
50
60
ns
Maximum column address access time
25
30
ns
Maximum
CAS
access time
12
15
ns
Maximum output enable (
OE
) access time
13
15
ns
Minimum read or write cycle time
80
100
ns
Minimum fast page mode cycle time
25
30
ns
Maximum operating current
120
110
mA
Maximum CMOS standby current
1.0
1.0
mA
Pin designation