參數(shù)資料
型號(hào)： AS5013-IQFT-1000
廠商： ams
文件頁(yè)數(shù)： 12/32頁(yè)
文件大小： 1012K
描述： IC ENCODER HALL SENSOR 16-QFN
標(biāo)準(zhǔn)包裝： 1,000
系列： EasyPoint™
傳感范圍： 30mT ~ 120mT
類型： 專用型
電源電壓： 2.7 V ~ 3.6 V
電流 - 電源： 190µA
輸出類型： 數(shù)字式，開漏極
特點(diǎn)： 低功率
工作溫度： -20°C ~ 80°C
封裝/外殼： 16-UQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 16-QFN（4x4）
包裝： 帶卷 (TR)
www.ams.com/AS5013
Revision 1.11
12 - 32
AS5013
Datasheet - Detailed Description
7.5.4   I睠 Modes
The AS5013 supports the I睠 bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a
receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A
master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the
bus. The AS5013 operates as a slave on the I睠 bus. Connections to the bus are made through the open-drain I/O lines SDA and the input SCL.
Clock stretching is not included.
Automatic Increment of Address Pointer.
The AS5013 slave automatically increments the address pointer after each byte transferred. The increase of the address pointer is independent
from the address being valid or not.
Invalid Addresses.
If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or write cycle is possible.
The address pointer is increased after each byte.
Reading.
When reading from a wrong address, the AS5013 slave data returns all zero. The address pointer is increased after each byte. Sequential read
over the whole address range is possible including address overflow.
Writing.
A write to a wrong address is not acknowledged by the AS5013 slave, although the address pointer is increased. When the address pointer
points to a valid address again, a successful write access is acknowledged. Page write over the whole address range is possible including
address overflow.
The following bus protocol has been defined:
n Data transfer may be initiated only when the bus is not busy.
n During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH 
are interpreted as start or stop signals.
Accordingly, the following bus conditions have been defined:
t
rCL1
Rise time of SCLH signal
after repeated START
condition and after an
acknowledge bit
External pull-up
source of 3mA
-
-
10
80
20
160
ns
t
R
Rise Time of SDA and
SCL Signals
20+0.1C
B
120
-
-
-
-
ns
t
F
Fall time of SDA and SCL
signals
20+0.1C
B
120
-
-
-
-
ns
t
SU;STO
Setup Time for STOP
Condition
600
-
160
-
160
-
ns
V
nL
Noise margin at LOW level
For each connected
device (including
hysteresis)
0.1VDDp
-
0.1VDDp
-
0.1VDDp
-
V
V
nH
Noise margin at HIGH
level
0.2VDDp
-
0.2VDDp
-
0.2VDDp
-
V
1. For bus line loads C
B
 between 100pF and 400 pF the timing parameters must be linearly interpolated.
2. After this time the first clock is generated.
3. A device must internally provide a minimum hold time (300n for Fast-mode, 80ns / max 150ns for High-speed mode) for the SDA signal
(referred to the VIHmin of the SCL) to bridge the undefined region of the falling edge of SCL.
4. A fast-mode device can be used in standard-mode system, but the requirement t
SU;DAT
 = 250ns must then be met. This is automatically
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line t
Rmax
 + t
SU;DAT
 = 1000 + 250 = 1250ns before the SCL line is released.
Symbol
Parameter
Condition
Fast-mode
HS-mode C
B
=100pF
HS-mode
C
B
=400pF
1
Unit
Min
Max
Min
Max
Min
Max
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