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參數(shù)資料
| 型號： | AS5SS128K36 |
| 英文描述： | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT |
| 中文描述： | 128K的× 36的SSRAM同步ZBL SRAM的流過式輸出 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 224K |
| 代理商： | AS5SS128K36 |
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
AS5SS128K36
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
READ/WRITE TIMING
READ/WRITE TIMING PARAMETERS
MIN
11
MAX
MIN
12
MAX
t
KHKH
t
KF
90
83
t
KHKL
3.0
3.0
t
KLKH
3.0
3.0
t
KHQV
8.5
9.0
t
KHQX
3.0
3.0
t
KHQX1
3.0
3.0
t
KHQZ
5.0
5.0
t
GLQV
5.0
5.0
t
GLQX
0
0
SYMBOL
-12
-11
MIN
MAX
5.0
MIN
MAX
5.0
t
GHQZ
t
AVKH
2.2
2.5
t
EVKH
2.2
2.5
t
CVKH
2.2
2.5
t
DVKH
2.2
2.5
t
KHAX
0.5
0.5
t
KHEX
0.5
0.5
t
KHCX
0.5
0.5
t
GLDX
0.5
0.5
SYMBOL
-12
-11
NOTE:
1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0=linear, 1=interleaved). BURST operations are optional.
3. CE\ represents three signals. When CE\ = 0, it represents CE\ = 0, CE2\ = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
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123456789
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12
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1234567890
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12345678
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A1
t
AVKH
t
KHAX
1234
1234
1234
A2
11234567
11234567
11234567
123
123
123
A3
123
123
123
A4
t
KHQV
11234567
11234567
11234567
123
123
123
A5
123
123
123
A6
123
123
123
A7
11234567
11234567
11234567
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1234
D(A1)
t
DVKH
t
KHDX
123
123
123
D(A2)
123
123
123
D(A2+1)
123
123
123
123
Q(A3)
12
12
12
12
Q(A4)
12
12
12
12
Q(A4+1)
123
123
123
123
D(A5)
12
12
12
12
Q(A6)
123
123
123
123
123
123
123
123
D(A7)
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4 +1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
123
123
123
Don’t Care
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1234
Undefined
CLK
CLE\
CE\
ADV/LD\
R/W\
BWx\
ADDRESS
DQ
OE\
COMMAND
1
2 3 4 5 6 7 8 9 10
t
KHKH
t
KHKL
t
t
KHEX
t
KHCX
t
KHQX1
t
KHQX
t
GHQZ
t
GLQX
t
GLQV
t
KHQX
t
KHQZ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS5SS128K36DQ-10 | x36 Fast Synchronous SRAM |
| AS5SS128K36DQ-11 | x36 Fast Synchronous SRAM |
| AS5SS128K36DQ-11IT | x36 Fast Synchronous SRAM |
| AS6UA25617 | 1.65V to 3.6V 256K x 16 Intelliwatt low power CMOS SRAM with two chip enables |
| AS6UA51216 | 1.65V to 3.6V 512K x 16 Intelliwatt low power CMOS SRAM with one chip enable |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS5SS128K36DQ-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| AS5SS128K36DQ-11 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| AS5SS128K36DQ-11/IT | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT |
| AS5SS128K36DQ-11/XT | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT |
| AS5SS128K36DQ-11IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
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