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參數(shù)資料
| 型號： | AS5SS256K18DQ-10/XT |
| 廠商： | AUSTIN SEMICONDUCTOR INC |
| 元件分類： | SRAM |
| 英文描述： | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| 中文描述： | 256K X 18 STANDARD SRAM, 10 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 135K |
| 代理商： | AS5SS256K18DQ-10/XT |
AS5SS256K18
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD Supply Relative to VSS............-0.5V to +4.6V
Voltage on V
DDQ Supply Relative to VSS.........-0.5V to +4.6V
Storage Temperature (plastic) .....................-55
°C to +125°C
Max Junction Temperature**.......................................+150
°C
Short Circuit Output Current..........…...........................100mA
*Stresses greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
**Maximum junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(-55o
A < +125
oC and -40oC<T
A<+85
oC; V
DD = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
VIH
2.0
VDD +0.3
V
1, 2
Input Low (Logic 0) Voltage
VIL
-0.3
0.8
V
1, 2
Input Leakage Current
(0V<VIN<VDD)
ILI
-2
2
Α
3
Output Leakage Current
Output(s) disabled;
0V<VIN<VDD
ILO
-2
2
Α
Output High Voltage
IOH = -4.0mA
VOH
2.4
--
V
1, 4
Output Low Voltage
IOL = 8.0 mA
VOL
--
0.5
V
1, 4
Supply Voltage
VDD
3.135
3.6
V
1
Isolated Output Buffer Supply
VDDQ
3.135
3.6
V
1, 5
NOTES:
1. All voltages referenced to VSS (GND)
2. Overshoot: V
IH < +4.6V for t <
tKC/2 for I < 20mA
Undershoot: V
IL > -0.7V for t <
tKC/2 for I < 20mA
Power-up: V
IH < +3.6V and VDD<3.135V for t < 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10A.
4. The load used for V
OH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher then the stated DC values.
5. V
DDQ should never exceed VDD. VDD and VDDQ can be connected together, for 3.3V I/O operation only.
6. This parameter is sampled.
CAPACITANCE
DESCRIPTION
CONDITIONS
SYM
MAX
UNITS
NOTES
Control Input Capacitance
CI
4pF
6
Input/Output Capacitance (DQ)
CO
5pF
6
Address Capacitance
CA
3.5
pF
6
Clock Capacitance
CCK
3.5
pF
6
TA = 25°C; f = 1MHz;
VDD = 3.3V
THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYM
TYP
UNITS
NOTES
Thermal Resistance
(Junction to Ambient)
θJA
46
°C/W
6
Thermal Resistance
(Junction to Top of Case)
θJC
2.8
°C/W
6
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
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