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參數(shù)資料
| 型號： | AS5SS256K18DQ-9/XT |
| 廠商： | AUSTIN SEMICONDUCTOR INC |
| 元件分類： | SRAM |
| 英文描述： | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| 中文描述： | 256K X 18 STANDARD SRAM, 8.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大小： | 135K |
| 代理商： | AS5SS256K18DQ-9/XT |
AS5SS256K18
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
AC TEST CONDITIONS
OUTPUT LOADS
VIH = (VDD/2.2) + 1.5V
VIL = (VDD/2.2) - 1.5V
Input rise and fall times
1ns
Input timing reference levels
VDD/2.2
Output reference levels
VDDQ/2.2
Output load
See Figures 1 and 2
Input pulse levels
3.3v
DQ
Fig. 2 OUTPUT LOAD EQUIVALENT
351
5 pF
317
Fig. 1 OUTPUT LOAD EQUIVALENT
DQ
50
Z
0=50
Vt = 1.5V
LOAD DERATING CURVES
ASI’s 256K x 18 Synchronous Burst SRAM timing is dependent upon
the capacitive loading on the outputs.
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down” mode in which the
device is deselected and current is reduced to I
SB2Z.
The duration of
SNOOZE MODE is dictated by the length of time ZZ is in a HIGH
state. After the device enters SNOOZE MODE, all inputs except ZZ
become gated inputs and are ignored.
ZZ is an asynchronous, active HIGH input that causes the device to
enter SNOOZE MODE. When ZZ becomes a logic HIGH, I
SB2Z
is
guaranteed after the setup time t
ZZ
is met. Any READ or WRITE
operation pending when the device enters SNOOZE MODE is not
quaranteed to complete successfully. Therefore, SNOOZE MODE
must not be initiated until valid pending operations are completed.
* Except ZZ
1234
Don’t Care
SNOOZE MODE WAVEFORM
DESCRIPTION
CONDITIONS
SYM
MIN
MAX
UNITS
NOTES
Current during SNOOZE MODE
ZZ > VIH
ISB2Z
10
mA
ZZ active to input ignored
tZZ
tKC
ns
1
ZZ inactive to input sampled
tRZZ
tKC
ns
1
ZZ active to snooze current
tZZI
tKC
ns
1
ZZ inactive to exit snooze current
tRZZI
0ns
1
SNOOZE MODE ELECTRICAL CHARACTERISTICS
NOTE: 1. This parameter is sampled.
12345
1234567890
1
12
t
ZZ
t
RZZ
t
ZZI
I
SB2
t
RZZI
CLK
ZZ
I
SUPPLY
ALL INPUTS*
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