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參數(shù)資料
| 型號(hào)： | AS6UA51216 |
| 英文描述： | 1.65V to 3.6V 512K x 16 Intelliwatt low power CMOS SRAM with one chip enable |
| 中文描述： | 1.65V至3.6V的為512k × 16 Intelliwatt低功耗CMOS SRAM的同一個(gè)芯片上，使 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 216K |
| 代理商： | AS6UA51216 |
6
ALLIANCE SEMICONDUCTOR
7/14/00
AS6UA25617
Data retention characteristics (over the operating range)
13,5
Parameter
VCC for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
Data retention waveform
AC test loads and waveforms
Notes
1
2
3
4
5
6
7
8
9
10 CS1 or WE must be HIGH or CS2 LOW during address transitions. Either CS1 or WE asserting HIGH terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 1.2V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at HIGH Z and LOW Z parameters, where C = 5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CS1 is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Condtions
.
t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CS1 and OE are LOW and CS2 is HIGH for read cycle.
Address valid prior to or coincident with CS1 transition LOW and CS2 HIGH.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Sym
V
DR
I
CCDR
t
CDR
t
R
Test conditions
V
CC
= 1.2V
CS1
≥
V
CC
– 0.1V or
UB = LB > V
CC
– 0.1V
V
IN
≥
V
CC
– 0.1V or
V
IN
≤
0.1V
Min
1.2V
–
0
t
RC
Max
3.6
2
–
–
Unit
V
mA
ns
ns
Parameters
R1
R2
R
TH
V
TH
3.0V
1105
1550
645
1.75V
2.5V
16670
15380
8000
1.2V
2.0V
15294
11300
6500
0.85V
Unit
Ohms
Ohms
Ohms
Volts
V
CC
CS1
t
R
t
CDR
Data retention mode
V
CC
V
CC
V
DR
≥
1.2V
V
IH
V
IH
V
DR
CS2
t
R
t
CDR
V
IH
V
IH
V
DR
V
CC
R1
R2
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
V
CC
R1
R2
OUTPUT
5 pF
ALL INPUT PULSES
(b)
10%
90%
10%
90%
GND
V
CC
Typ
< 5 ns
(c)
Thevenin equivalent:
OUTPUT
R
TH
V
INCLUDING
JIG AND
SCOPE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS6VA2516-TC | x16 SRAM |
| AS6VA2516-BC | x16 SRAM |
| AS6WA5128 | 3.0V to 3.6V 512K x 8 Intelliwatt low-power CMOS SRAM |
| AS6WA5128-BC | x8 SRAM |
| AS6WA5128-BI | x8 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS6UA51216-BC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:1.65V to 3.6V 512K】16 Intelliwatt low power CMOS SRAM with one chip enable |
| AS6UA51216-BI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:1.65V to 3.6V 512K】16 Intelliwatt low power CMOS SRAM with one chip enable |
| AS6UA51216-TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:1.65V to 3.6V 512K】16 Intelliwatt low power CMOS SRAM with one chip enable |
| AS6UA51216-TI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:1.65V to 3.6V 512K】16 Intelliwatt low power CMOS SRAM with one chip enable |
| AS6UA5128 | 制造商:SEMICOA 制造商全稱:SEMICOA 功能描述:2.3V to 3.6V 512K】8 Intelliwatt low-power CMOS SRAM |
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