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參數(shù)資料
| 型號(hào)： | AS7C33512NTD18A-166BC |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 9 ns, PBGA119 |
| 封裝： | 14 X 20 MM, BGA-119 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 299K |
| 代理商： | AS7C33512NTD18A-166BC |
AS7C33512NTD16A
AS7C33512NTD18A
3/11/02;
v.1.8H
Alliance Semiconductor
4 of 12
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
Signal descriptions
Signal
I/O
Properties
Description
CLK
I
CLOCK
Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
CEN
I
SYNC
Clock enable. When de-asserted HIGH, the clock input signal is masked.
A, A0, A1
I
SYNC
Address. Sampled when all chip enables are active and ADV/LD is asserted.
DQ[a,b]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0, CE1,
CE2
ISYNC
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is HIGH.
ADV/LD
ISYNC
Advance or Load. When sampled HIGH, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When LOW, a new
address is loaded.
R/W
ISYNC
A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is HIGH.
BW[a,b]
ISYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
OE
I
ASYNC
Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO
ISTATIC
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This input should be static when the
device is in operation.
FT
ISTATIC
Flow-through mode.When low, enables single register flow-through mode. Connect to VDD
if unused or for pipelined operation.
ZZ
I
ASYNC
Snooze. Places device in low power mode; data is retained. Connect to VSS if unused.
NC
-
No connects. Note that pin 84 will be used for future address expansion to 18Mb density.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to GND
VDD, VDDQ
–0.5
+4.6
V
Input voltage relative to GND (input pins)
VIN
–0.5
VDD + 0.5
V
Input voltage relative to GND (I/O pins)
VIN
–0.5
VDDQ + 0.5
V
Power dissipation
PD
–1.8
W
DC output current
IOUT
–50
mA
Storage temperature (plastic)
Tstg
–65
+150
°C
Temperature under bias
Tbias
–65
+135
°C
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33512NTD18A-166TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD18A-166TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD18A-166TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD18A-166TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD32A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
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