參數(shù)資料
型號: AS7C3364FT36B-65TQCN
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: SRAM
英文描述: 64K X 36 STANDARD SRAM, 6.5 ns, PQFP100
封裝: 14 X 20 MM, LEAD FREE, TQFP-100
文件頁數(shù): 16/19頁
文件大?。?/td> 417K
代理商: AS7C3364FT36B-65TQCN
AS7C3364FT32B
2/8/05; v.1.2
Alliance Semiconductor
P. 6 of 19
AS7C3364FT36B
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Write enable truth table (per byte)
1
1
Key: X = don’t care, L = low, H = high, n = a, b, c, d;
BWE, BWn = internal write signal.
Function
GWE
BWE
BWa
BWb
BWc
BWd
Write All Bytes
L
X
XXX
X
H
L
LL
Write Byte a
HL
LH
H
Write Byte c and d
HL
H
L
Read
HH
XXX
X
H
L
HHH
H
Operation
ZZ
OE
I/O Status
Snooze mode
H
X
High-Z
Read
L
Dout
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Interleaved burst address (LBO = 1)
Linear burst address (LBO = 0)
A1 A0
1
st Address
0 00 11 0
1 1
1
st Address
0 0
0 11 01 1
2nd Address
0 10 01 1
1 0
2nd Address
0 1
1 01 10 0
3rd Address
1 01 10 0
0 1
3rd Address
1 0
1 10 00 1
4
th Address
1 11 00 1
0 0
4
th Address
1 1
1 00 11 0
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