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Andigilog, Inc. 2006
www.andigilog.com
August 2006 - 70A05003
aSC7512
set, the master must perform a repeat start condition that
indicates to the aSC7512 that a read is about to occur. It is
important to note that if the repeat start condition does not
occur, the aSC7512 will assume that a write is taking place,
and the selected register will be overwritten by the
upcoming data on the data bus. The read sequence is
described in Figure 4. After the start condition, the master
must again send the device address and read/write bit.
This time the R/
W
bit must be set to 1 to indicate a read.
The rest of the read cycle is the same as described in the
previous paragraph for reading from a preset pointer
location.
If the pointer is already pointing to the desired register, the
master can read from that register by setting the R/
W
bit
(following the slave address) to a 1. After sending an ACK,
the aSC7512 will begin transmitting data during the
following clock cycle. After receiving the 8 data bits, the
master device should respond with a NACK followed by a
stop condition.
If the master is reset while the aSC7512 is in the process of
being read, the master should perform an SMBus reset.
This is done by holding the data or clock low for more than
35ms, allowing all SMBus devices to be reset. This follows
the SMBus 2.0 specification of 25-35ms.
When the aSC7512 detects an SMBus reset, it will prepare
to accept a new start sequence and resume
communication from a known state.
1
A7
A6
A5
A4
A3
A2
A1
A0
Start
SMBus Device Address Byte (58h)
Register Address Byte
A
A
ACK
from
aSC7512
ACK
from
aSC7512
SCL
SDA
1 0
0
1
S
0
0
1
9
1
9
A7
A6
A5
A4
A3
A2
A1
A0
Start
SMBus Device Address Byte (58h)
Register Address Byte
R/W A
A
ACK
from
aSC7512
ACK
from
aSC7512
SCL
1
9
1
9
Stop
by
Master
1
9
D7
D6
D5
D4
D3
D2 D1
D0
Register Data Byte
A
ACK
from
aSC7512
Stop
By
Master
R/W
1 0
0
1
S
0
0
SDA
1
D7
D6
D5
D4
D3
D2
D1
D0
Re-start
Register Data Byte
A
N
R/W
SMBus Device Address Byte (58h)
ACK
from
aSC7512
NACK
from
Master
Stop
by
Master
Register Address
Pointer Set
(Figure 2.)
without stop by Master
+
1
9
1
9
1 0
0
1
S
0
0
1
Figure 2 Register Address Pointer Set
Figure 3 Register Write
Figure 4 Register Read