參數(shù)資料
型號(hào)： ASC7621QS24
廠商： Electronic Theatre Controls, Inc.
英文描述： HARDWARE MONITOR WITH INTEGRATED FAN CONTROL
中文描述： 五金顯示器整合了風(fēng)扇控制
文件頁(yè)數(shù)： 8/50頁(yè)
文件大小： 565K
代理商： ASC7621QS24
P
P
- 8 -
Andigilog, Inc. 2006
www.andigilog.com
October 2006 - 70A06010
aSC7621
Control Communication
SMBus
The aSC7621 is compatible with devices that are compliant
to the SMBus 2.0 specifications. More information on this
bus can be found at
http://www.smbus.org/
. Compatibility
of SMBus2.0 to other buses is discussed in the SMBus 2.0
specification.
General Operation
Writing to and reading from the aSC7621 registers is
accomplished via the SMBus-compatible two-wire serial
interface. SMBus protocol requires that one device on the
bus initiate and control all read and write operations. This
device is called the “master” device. The master device
also generates the SCL signal that is the clock signal for all
other devices on the bus. All other devices on the bus are
called “slave” devices. The aSC7621 is a slave device.
Both the master and slave devices can send and receive
data on the bus.
During SMBus operations, one data bit is transmitted per
clock cycle. All SMBus operations follow a repeating nine
clock-cycle pattern that consists of eight bits (one byte) of
transmitted data followed by an acknowledge (ACK) or not
acknowledge (NACK) from the receiving device. Note that
there are no unused clock cycles during any operation—
therefore there must be no breaks in the stream of data
and ACKs / NACKs during data transfers.
For most operations, SMBus protocol requires the SDA line
to remain stable (unmoving) whenever SCL is high — i.e.
any transitions on the SDA line can only occur when SCL is
low. The exceptions to this rule are when the master device
issues a start or stop condition. Note that the slave device
cannot issue a start or stop condition.
SMBus Definitions
The following are definitions for some general SMBus
terms:
Start Condition:
This condition occurs when the SDA line
transitions from high to low while SCL is high. The master
device uses this condition to indicate that a data transfer is
about to begin.
Stop Condition:
This condition occurs when the SDA line
transitions from low to high while SCL is high. The master
device uses this condition to signal the end of a data
transfer.
Acknowledge
and
Not Acknowledge:
When data are
transferred to the slave device it sends an “acknowledge”
(ACK) after receiving each byte. The receiving device
sends an ACK by pulling SDA low for one clock. Following
the last byte, a master device sends a "not acknowledge"
(NACK) followed by a stop condition. A NACK is indicated
by forcing SDA high during the clock after the last byte.
Slave Address
aSC7621 is designed to be used primarily in desktop
systems that require only one monitoring device. If only one
aSC7621 is used on the motherboard, the designer should
be sure that the
AddressEnable
/PWM3 pin is High during
the first SMBus communication addressing the aSC7621.
AddressEnable
/PWM3 is an open drain I/O pin that at
power-on defaults to the input state of
AddressEnable
. A
maximum of 10k pull-up resistance on
AddressEnable
/PWM3 is required to assure that the
SMBus address of the device will be locked at 010 1110b,
which is the default address of the aSC7621.
During the first SMBus communication TACH4 and PWM3
can be used to change the SMBus address of the aSC7621
to 0101101b or 0101100b. aSC7621 address selection
procedure:
A 10k
pull-down resistor to ground on the
AddressEnable
/PWM3 pin is required. Upon power
up, the aSC7621 will be placed into
AddressEnable
mode and assign itself on SMBus
address according to the state of the Address Select
input. The aSC7621 will latch the address during the
first valid SMBus transaction in which the first five bits
of the targeted address match those of the aSC7621
address, 0 1011b. This feature eliminates the
possibility of a glitch on the SMBus interfering with
address selection. When the
AddressEnable
/PWM3
pin is not used to change the SMBus address of the
aSC7621, it will remain in a high state until the first
communication with the aSC7621. After the first
SMBus transaction is completed PWM3 and TACH4
will return to normal operation.
Address
Enable
SMBus
Address
Binary
Address
Select
Board Imple-
mentation
Hex
0
0
Both pins pulled
to ground
through a 10 k
resistor
Address Select
pulled to 3.3V
and
AddressEnable
pulled to GND
through a 10 k
resistor
010
1100
2Ch
0
1
010
1101
2Dh
1
X
AddressEnable
pulled to 3.3V
through a 10 k
resistor
010
1110
2Eh
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