- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄166373 > ASI-L67201L-60 (ATMEL WIRELESS MICROCONTROLLERS) 512 X 9 OTHER FIFO, 60 ns, PQCC32 PDF資料下載
參數(shù)資料
| 型號(hào)： | ASI-L67201L-60 |
| 廠商： | ATMEL WIRELESS MICROCONTROLLERS |
| 元件分類： | FIFO |
| 英文描述： | 512 X 9 OTHER FIFO, 60 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 146K |
| 代理商： | ASI-L67201L-60 |
L 67201/L 67202
MATRA MHS
Rev. C (10/11/95)
3
Pin Names
NAMES
DESCRIPTION
I0–8
Inputs
Q0–8
Outputs
W
Write Enable
R
Read Enable
RS
Reset
EF
Empty Flag
NAMES
DESCRIPTION
FF
Full Flag
XO/HF
Expansion Out/Half–Full Flag
XI
Expansion IN
FL/RT
First Load/Retransmit
VCC
Power Supply
GND
Ground
Signal Description
Data In (I0 - I8)
Data inputs for 9 - bit data
Reset (RS)
Reset occurs whenever the Reset (RS) input is taken to a
low state. Reset returns both internal read and write
pointers to the first location. A reset is required after
power-up before a write operation can be enabled. Both
the Read Enable (R) and Write Enable (W) inputs must be
in the high state during the period shown in figure 1 (i.e.
tRSS before the rising edge of RS) and should not change
until tRSR after the rising edge of RS. The Half-Full flag
(HF will be reset to high after Reset (RS).
Figure 1. Reset.
Notes :
1. EF, FF and HF may change status during reset, but flags will be valid at tRSC.
2. W and R = VIH around the rising edge of RS.
Write Enable (W)
A write cycle is initiated on the falling edge of this input
if the Full Flag (FF) is not set. Data set-up and hold times
must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the
Ram array, regardless of any current read operation.
Once half of the memory is filled, and during the falling
edge of the next write operation, the Half-Full Flag (HF)
will be set to low and remain in this state until the
difference between the write and read pointers is less than
or equal to half of the total available memory in the
device. The Half-Full Flag (HF) is then reset by the rising
edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go low,
inhibiting further write operations. On completion of a
valid read operation, the Full Flag (FF) will go high after
TRFF, allowing a valid write to begin. When the FIFO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ATIR0721DS | POSITION, LINEAR SENSOR-DIFFUSE, 1-1mm, 3mA, RECTANGULAR, SURFACE MOUNT |
| ATIR0821DS | POSITION, LINEAR SENSOR-DIFFUSE, 1-1mm, 3mA, RECTANGULAR, THROUGH HOLE MOUNT |
| ATL80/25-256VM | FPGA, 15600 GATES |
| ATL80/25-256QM | FPGA, 15600 GATES |
| ATL80/25-256AM | FPGA, 15600 GATES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASILUFC51 | 制造商:Schneider Electric 功能描述:AS-I/2 COMMUNICATION MODULE 制造商:SCHNEIDER ELECTRIC 功能描述:COMMUNICATION MODULE - FOR TESYS U |
| ASI-MA40232-119 | 制造商:ASI 制造商全稱:ASI 功能描述:SILICON DETECTOR DIODE |
| ASIMM8006 | 制造商:ASI 制造商全稱:ASI 功能描述:NPN SILICON HIGH FREQUENCY TRANSISTOR |
| ASIMRAL1720-9 | 制造商:ASI 制造商全稱:ASI 功能描述:NPN SILICON RF POWER TRANSISTOR |
| ASIMRAL2023-6 | 制造商:ASI 制造商全稱:ASI 功能描述:NPN SILICON RF POWER TRANSISTOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。