參數(shù)資料
型號: ASM1232LPU-T
廠商: ON SEMICONDUCTOR
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封裝: MSOP-8
文件頁數(shù): 8/13頁
文件大?。?/td> 377K
代理商: ASM1232LPU-T
ASM1232LP/LPS
Rev. 2 | Page 4 of 13 | www.onsemi.com
Detailed Description
The ASM1232LP/LPS monitors the microprocessor or
micro controller power supply and generates reset signal,
both active HIGH and Active LOW, that halt processor
operation whenever the power supply voltage levels are
outside a predetermined tolerance.
RESET and RESET outputs
RESET is an active HIGH signal developed by a CMOS
push-pull output stage and is the logical opposite to
RESET.
RESET is an active LOW signal. It is developed with an
open
drain driver. A pull up resistor of typical value 10kΩ
to 50kΩ is required to connect with the output.
Trip Point Tolerance Selection
The TOL input is used to determine the level VCC can vary
below 5V without asserting a reset. With TOL connected
to VCC, RESET and RESET become active whenever VCC
falls below 4.5V. RESET and RESET become active
when the VCC falls below 4.75V if TOL is connected to
ground.
After VCC has risen above the trip point set by TOL,
RESET and RESET remain active for a minimum time
period of 250ms. On power-down, once VCC falls below
the reset threshold RESET stays LOW and is guaranteed
to be 0.4V or less until VCC drops below 1.2V. The active
HIGH reset signal is valid down to a VCC level of 1.2V
also.
Tolerance
Select
Tolerance
TRIP Point Voltage
(V)
Min
Nom
Max
TOL = VCC
10%
4.25
4.37
4.49
TOL = GND
5%
4.5
4.62
4.74
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