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參數(shù)資料
| 型號： | ASM161JEUS/T |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4 |
| 封裝： | PLASTIC, SOT-143, 4 PIN |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 341K |
| 代理商： | ASM161JEUS/T |
ASM161 and ASM162
Rev. 2 | Page 3 of 9 | www.onsemi.com
Pin Description
Pin #
Pin
Name
Function
ASM161
ASM162
1
GND
Ground.
2
-
RESET
Active-LOW, open-drain reset output. RESET remains LOW while VCC is
below the reset threshold and for 800ms minimum after VCC rises above the
reset threshold. An external pull-up resistor is needed.
-
2
RESET
Active HIGH reset output. RESET remains HIGH while VCC is below the
reset threshold and for 800ms after VCC rises above the reset threshold.
3
MR
Manual reset input. A negative going edge transition on MR asserts reset.
Reset remains asserted for one reset time-out period (800ms min). This
active-LOW input has an internal pull-up resistor. It can be driven from a
TTL or CMOS logic line or shorted to ground with a switch. Leave open if
unused.
4
VCC
Power supply input voltage.
Detailed Description
The reset function ensures the microprocessor is properly
reset and powers up into a known condition after a power
failure.
Reset Timing
A reset is generated whenever the supply voltage is
below the threshold level (VCC < VTH). The reset duration
is at least 800ms after VCC has risen above the reset
threshold and is guaranteed to be no more than
2
seconds. The rest signal remains active as long as the
monitored supply voltage is below the internal threshold
voltage.
The ASM161 has an open-drain, active LOW RESET
output (which is guaranteed to be in the correct state for
VCC down to 1.1V). The ASM161 uses an external pull-up
resistor. Output leakage current is under 1
μA. A high
resistance value can be used to minimize current drain.
The ASM162 generates an active-HIGH RESET output.
Part
Number
Reset Polarity
ASM161
LOW (use external pull-up resistor)
ASM162
HIGH
Manual Reset
The ASM161/162 have a unique manual reset circuit. A
negative going edge transition on MR initiates the reset.
A manual reset generates a single reset pulse of fixed
length. The output-reset pulse remains asserted for the
Reset Active Time-Out Period tRP and then clears. Once
the reset pulse is completed, the MR input remains
disabled for at least 49
μS but not more than 122μS. This
period is specified as tMRD.
During the MR disabled period, the microcontroller is
guaranteed a time period free of new manual reset
signals. This period can be used to refresh critical DRAM
contents or other system tasks.
The MR pin must be taken HIGH and LOW again after
the tMRD period has been completed to initiate another
reset pulse.
The manual reset input has an internal 20kΩ pull-up
resistor. MR can be left open if not used.
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