參數(shù)資料
型號: ASM5I23S05AF-1H-08-TT
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: LM4050 Precision Micropower Shunt Voltage Reference; Package: SOT-23; No of Pins: 3
中文描述: 23S SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝: 4.40 MM, LEAD FREE, TSSOP-8
文件頁數(shù): 1/18頁
文件大?。?/td> 388K
代理商: ASM5I23S05AF-1H-08-TT
ASM5P23S09A
November 2004
ASM5P23S05A
rev 1.3
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
REF
ASM5P23S05A
3.3V ‘SpreadTrak’ Zero Delay Buffer
General Features
15 MHz to 133 MHz operating range, compatible
with CPU and PCI bus frequencies.
Zero input - output propagation delay.
Multiple low-skew outputs.
Output-output skew less than 250 pS.
Device-device skew less than 700 pS.
One input drives 9 outputs, grouped as 4+4+1
(ASM5P23S09A).
One input drives 5 outputs (ASM5P23S05A).
Less than 200 pS cycle-to-cycle jitter is compatible
with Pentium
based systems.
Test Mode to bypass PLL (ASM5P23S09A only,
refer Select Input Decoding Table).
Available in 16-pin, 150-mil SOIC and 4.4 mm
TSSOP packages for ASM5P23S09A and in
8-pin, 150-mil SOIC and 4.4 mm TSSOP
packages for ASM5P23S05A.
3.3V operation
Advanced 0.35< CMOS technology.
‘SpreadTrak’.
Functional Description
ASM5P23S09A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks with Spread
Spectrum capability. It is available in a 16-pin package. The
ASM5P23S05A
is
the
eight-pin
version
of
the
ASM5P23S09A. It accepts one reference input and drives
out five low-skew clocks.
The -1H version of the ASM5P23SxxA operates at up to
133 MHz frequency, and has higher drive than the -1
device. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The ASM5P23S09A has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. If all the output clocks are
not required, Bank B can be three-stated. The select input
also allows the input clock to be directly applied to the
outputs for chip and system testing purposes.
Multiple ASM5P23S09A and ASM5P23S05A devices can
accept the same input clock and distribute it. In this case
the skew between the outputs of the two devices is
guaranteed to be less than 700 pS.
All outputs have less than 200 pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250 pS, and the output to output skew is
guaranteed to be less than 250 pS.
The ASM5P23S09A and the ASM5P23S05A are available
in two different configurations, as shown in the ordering
information table. The ASM5P23SxxA-1 is the base part.
The ASM5P23SxxA-1H is the high drive version of the -1
part and its rise and fall times are much faster than -1 part.
Block Diagram
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
REF
S1
S2
Select Input
MUX
ASM5P23S09A
Decoding
PLL
相關(guān)PDF資料
PDF描述
ASM5I23S09AF-1H-16-TR LM4051 Precision Micropower Shunt Voltage Reference; Package: SOT-23; No of Pins: 3
ASM5I23S09AF-1H-16-TT LM4051 Precision Micropower Shunt Voltage Reference; Package: SOT-23; No of Pins: 3
ASM5P23S05A-1-08-TT LM4125 Precision Micropower Low Dropout Voltage Reference; Package: SOT-23; No of Pins: 5
ASM5P23S05A-1H-08-TT 3.3V SpreadTrak Zero Delay Buffer
ASM5P23S05AF-1H-08-TT 3.3V SpreadTrak Zero Delay Buffer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ASM5I23S05AG-1-08-SR 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V ‘SpreadTrak’ Zero Delay Buffer
ASM5I23S05AG-1-08-ST 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V ‘SpreadTrak’ Zero Delay Buffer
ASM5I23S05AG-1-08-TR 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V ‘SpreadTrak’ Zero Delay Buffer
ASM5I23S05AG-1-08-TT 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V ‘SpreadTrak’ Zero Delay Buffer
ASM5I23S05AG-1H-08-SR 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V ‘SpreadTrak’ Zero Delay Buffer