參數(shù)資料
型號: ASM5I23S08AG-3-16-ST
廠商: Alliance Semiconductor Corporation
英文描述: LM4050 Precision Micropower Shunt Voltage Reference; Package: SOT-23; No of Pins: 3
中文描述: 3.3零延遲緩沖器
文件頁數(shù): 11/18頁
文件大?。?/td> 409K
代理商: ASM5I23S08AG-3-16-ST
September 2005
ASM5P23S08A
rev 1.4
3.3V ‘SpreadTrak’ Zero Delay Buffer
2 of 18
Notice: The information in this document is subject to change without notice.
Block Diagram
Select Input Decoding for ASM5P23S08A
S2
S1
Clock A1 - A4
Clock B1 - B4
Output Source
PLL Shut-Down
0
Three-state
PLL
Y
0
1
Driven
Three-state
PLL
N
1
0
Driven
1
Driven
Reference
Y
1
Driven
PLL
N
ASM5P23S08A Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
ASM5P23S08A-1
Bank A or Bank B
Reference
ASM5P23S08A-1H
Bank A or Bank B
Reference
ASM5P23S08A-2
Bank A
Reference
Reference /2
ASM5P23S08A-2
Bank B
2 X Reference
Reference
ASM5P23S08A-3
Bank A
2 X Reference
Reference or Reference
2
ASM5P23S08A-3
Bank B
4 X Reference
2 X Reference
ASM5P23S08A-4
Bank A or Bank B
2 X Reference
ASM5P23S08A-5H
Bank A or Bank B
Reference /2
Note:
1. Outputs are non- inverted on ASM5P23S08A-2 and ASM5P23S08A-3 in bypass mode, S2 = 1 and S1 = 0.
2. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the ASM5P23S08A-2.
/2
MUX
Select Input
Decoding
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Extra Divider (-2, -3)
PLL
/2
Extra Divider (-3, -4)
Extra Divider (-5H)
REF
S2
S1
FBK
ASM5P23S08A
相關(guān)PDF資料
PDF描述
ASM5I23S08AG-3-16-TR LM4050 Precision Micropower Shunt Voltage Reference; Package: SOT-23; No of Pins: 3
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ASM5I23S08AG-3-16-TT 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V Zero Delay Buffer
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ASM5I23S08AG-4-16-ST 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V ‘SpreadTrak’ Zero Delay Buffer
ASM5I23S08AG-4-16-TR 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V ‘SpreadTrak’ Zero Delay Buffer