參數(shù)資料
型號(hào): ASM5P2304B-1H-08-ST
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: 3.3V Zero Delay Buffer
中文描述: 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁(yè)數(shù): 9/13頁(yè)
文件大?。?/td> 376K
代理商: ASM5P2304B-1H-08-ST
September 2005
ASM5P2304B
rev 0.5
3.3V Zero Delay Buffer
5 of 13
Notice: The information in this document is subject to change without notice.
Switching Characteristics for ASM5P2304B Commercial Temperature Devices
Parameter
Description
Test Conditions
Min Typ Max Unit
1/t1
Output Frequency
30pF load, -1,-1H,-2, -2H devices
4
20
MHz
Duty Cycle
5= (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = 20MHz
30pF load
40.0 50.0 60.0
%
Duty Cycle
5 = (t2 / t1) * 100
(-1, -2,-1H, -2H)
Measured at 1.4V, FOUT = <20MHz
15pF load
45.0 50.0 55.0
%
t3
Output Rise Time
5
(-1, -2)
Measured between 0.8V and 2.0V
30pF load
2.20
nS
t3
Output Rise Time
5
(-1, -2)
Measured between 0.8V and 2.0V
15pF load
1.50
nS
t3
Output Rise Time
5
(-1H, -2H)
Measured between 0.8V and 2.0V
30pF load
1.50
nS
t4
Output Fall Time
5
(-1, -2)
Measured between 2.0V and 0.8V
30pF load
2.20
nS
t4
Output Fall Time
5
(-1, -2)
Measured between 2.0V and 0.8V
15pF load
1.50
nS
t4
Output Fall Time
5
(-1H, -2H)
Measured between 2.0V and 0.8V
30pF load
1.25
nS
Output-to-output skew on same bank
(-1, -2)
All outputs equally loaded
200
Output-to-output skew (-1H, -2H)
All outputs equally loaded
200
Output bank A -to- output bank B skew
(-1, -2H)
All outputs equally loaded
200
t5
Output bank A to output bank b skew
(-2)
All outputs equally loaded
400
pS
t6
Delay, REF Rising Edge to FBK Rising
Edge
5
Measured at VDD /2
0
±250
pS
t7
Device-to-Device Skew
5
Measured at VDD/2 on the FBK pins of
the device
0
500
pS
t8
Output Slew Rate
5
Measured between 0.8V and 2.0V using
Test Circuit #2
1
V/nS
Measured at 20MHz, loaded outputs,
15pF load
175
Measured at 20MHz, loaded outputs,
30pF load
200
tJ
Cycle-to-cycle jitter
5
(-1, -1H, -2H)
Measured at 20MHz, loaded outputs,
15pF load
100
pS
Measured at 20MHz, loaded outputs,
30pF load
400
tJ
Cycle-to-cycle jitter
5
(-2)
Measured at 20MHz, loaded outputs,
15pF load
375
pS
tLOCK
PLL Lock Time
5
Stable power supply, valid clock
presented on REF and FBK pins
1.0
mS
Note:
5. Parameter is guaranteed by design and characterization. Not 100% tested in production
.
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