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參數(shù)資料
| 型號： | ASM706JCUA |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | MICRO, SOP-8 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 305K |
| 代理商： | ASM706JCUA |
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Notice: The information in this document is subject to change without notice
3/3.3/4.0 V P Supervisor Circuits
ASM706 P/ R/ S/ T/ J
ASM708 R/ S/ T/ J
April 2005
rev 1.5
second countdown. Additional transitions at WDI will reset
the watchdog timer and initiate a new countdown sequence.
WDO will also become LOW and remain so, whenever the
supply voltage, VCC, falls below the device threshold level.
WDO goes HIGH as soon as VCC transitions above the
threshold. There is no minimum pulse width for WDO as
there is for the RESET outputs. If WDI is floated, WDO
essentially acts as a low supply voltage output indicator.
Power-failure Detection With Auxiliary Comparator
All devices have an auxiliary comparator with 1.25V trip point.
The output, PFO, is active LOW and the noninverting input is
PFI. This comparator can be used as a supply voltage
monitor with an external resistor voltage divider. As the
monitored voltage level falls, PFI is reduced causing the PFO
output to go LOW. Normally PFO interrupts the processor so
the system can be shut down in a controlled manner.
Application Information
Bi-directional Reset Pin Interfacing
The ASM706/8 can interface with P/C bi-directional reset
pins by connecting a 4.7k
resistor in series with the RESET
output and the P/C bi-directional reset pin.
Ensuring the RESET is Valid Down to VCC = 0V
When VCC falls below 1.2V, the ASM706R/S/T/J and 708R/S/
T/J RESET outputs no longer pull down; it becomes
indeterminate. To avoid the possibility that stray charges
could build up and force RESET to the wrong state, a pull-
down resistor should be connected to the RESET pin, thus
draining such charges to ground. The resistor value is not
critical. A100k
resistor will pull RESET to ground without
loading it.
Figure 2: Watchdog timing
0V
Supply Voltage
BUF
Buffered
RESET
VCC
ASM70x
GND
RESET
Input
C or P
4.7k
Bi-directional I/O Pin
Figure 3: Bi-directional reset pin interfacing
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