參數(shù)資料
型號: AT17C010-10PI
英文描述: Configuration EEPROM
中文描述: 配置EEPROM
文件頁數(shù): 7/18頁
文件大?。?/td> 236K
代理商: AT17C010-10PI
7
AT17C512/010/LV512/010
0944E
12/01
For details of ISP, please refer to the
Programming Specification for Atmel's AT17 and AT17A Series FPGA Configuration
EEPROMs
, available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0437.pdf.
Figure 3.
In-System Programming of AT17 Series for PSLI Applications
Notes:
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
Figure 4.
In-System Programming of AT17 Series for Xilinx/Lucent FPGA Applications
Notes:
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
3. An internal pull-up resistor is enabled here for DONE.
V
2
4
6
8
10
DATA
1
SCLK
3
5
7
9
SER_EN
CC
V
CC
V
CC
4.7 k
W
4.7 k
W
GND
AT17 Series Device
AT40K/AT40KAL/AT94K
DATA0
CCLK
CON
INIT
SER_EN
READY
(2)
DATA
CLK
CE
RESET/OE
(1)
RESET
GND
RESET
M2
M1
M0
4.7 k
W
V
CC
DIN
CCLK
DONE
(3)
INIT
AT17 Series Device
SER_EN
READY
(2)
DATA
CLK
CE
RESET/OE
(1)
PROGRAM
XILINX FPGA
GND
PROGRAM
M2
M1
M0
V
2
4
6
8
10
DATA
1
SCLK
3
5
7
9
SER_EN
CC
V
CC
V
CC
4.7 k
W
4.7 k
W
GND
CC
V
4.7 k
W
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