參數(shù)資料
型號(hào): AT17C020-10JI
英文描述: Configuration EEPROM
中文描述: 配置EEPROM
文件頁數(shù): 6/18頁
文件大?。?/td> 236K
代理商: AT17C020-10JI
6
AT17C512/010/LV512/010
0944E
12/01
Example Circuits
Figure 1.
AT17 Series Device for Programming PSLI Devices
Notes:
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
The FPGA CON/DONE output drives the CE input of the AT17 Series Configurator, while the RESET/OE input is driven by
the FPGA INIT pin. This connection works under all normal circumstances, even when the user aborts the configuration
before CON/DONE has gone High. A Low level on the RESET/OE input, during FPGA reset, clears the configurator
s inter-
nal address pointer so that the reconfiguration starts at the beginning.
Figure 2.
Drop-In Replacement of XC17/ATT17 PROMs for Xilinx/Lucent FPGA Applications
Notes:
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
3. An internal pull-up resistor is enabled here for DONE.
V
CC
DATA0
CCLK
CON
INIT
AT17 Series Device
SER_EN
READY
(2)
DATA
CLK
CE
RESET/OE
(1)
RESET
AT40K/AT40KAL/AT94K
GND
RESET
M2
M1
M0
4.7 k
W
V
CC
V
CC
DIN
CCLK
DONE
(3)
INIT
AT17 Series Device
SER_EN
READY
(2)
DATA
CLK
CE
RESET/OE
(1)
PROGRAM
XILINX FPGA
GND
PROGRAM
M2
M1
M0
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