參數(shù)資料
型號: AT17F040-30JU
廠商: Atmel
文件頁數(shù): 14/19頁
文件大小: 0K
描述: IC FLASH CONFIG 4M 20PLCC
標準包裝: 46
可編程類型: 閃存
存儲容量: 4Mb
電源電壓: 2.97 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 20-PLCC
包裝: 管件
產(chǎn)品目錄頁面: 609 (CN2011-ZH PDF)
配用: ATDH2225-ND - CABLE ISP FOR AT17
ATDH2200E-ND - CONFIGURATOR PROGRAM BOARD KIT
4
3039K–CNFG–2/08
AT17F040/080
3.
Block Diagram
4.
Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration device without requiring an external
intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the
address counter. When RESET/OE is driven Low, the configuration device resets its address
counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series
Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA
output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and
the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
Config. Page
Select
Power-on
Reset
Flash
Memory
Clock/Oscillator
Logic
2-wire Serial Programming
Serial Download Logic
Control Logic
CLK
CEO(A2)
DATA
CE
RESET/OE
SER_EN
CE/WE/OE
Data
Address
READY
PAGE_EN
PAGESEL0
PAGESEL1
Reset
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