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參數(shù)資料
| 型號： | AT17LV010-10CU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 25/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SRL CONFIG EEPROM 1M 8-LAP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 可編程類型： | 串行 EEPROM |
| 存儲容量： | 1Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-TDFN |
| 供應(yīng)商設(shè)備封裝： | 8-LAP（6x6） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 609 (CN2011-ZH PDF) |
| 配用： | ATDH2225-ND - CABLE ISP FOR AT17 ATDH2200E-ND - CONFIGURATOR PROGRAM BOARD KIT |
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8
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
4.10
A2
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
4.11
READY
Open collector reset state indicator. Driven Low during power-up reset, released when power-up
is complete. It is recommended to use a 4.7 k
pull-up resistor when this pin is used.
4.12
SER_EN
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to V
CC.
4.13
V
CC
3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.
5.
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The AT17LV Serial Configuration EEPROM has
been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil-
inx applications.
6.
Control of Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and
self-explanatory.
The DATA output of the AT17LV series configurator drives DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of the AT17LV series configurator.
The CEO output of any AT17LV series configurator drives the CE input of the next
configurator in a cascaded chain of EEPROMs.
SER_EN must be connected to V
CC (except during ISP).
The READY(1) pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
Note:
1. This pin is not available for the AT17LV65/128/256 devices.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AT17LV010-10CU SL383 | 制造商:Atmel Corporation 功能描述:EEPROM SERL-2WIRE 1MBIT 1M X 1 3.3V/5V 8PIN LAP - Tape and Reel |
| AT17LV010-10DP | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Space FPGA Configuration EEPROM |
| AT17LV010-10DP_05 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Space FPGA Configuration EEPROM |
| AT17LV010-10DP-E | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Space FPGA Configuration EEPROM |
| AT17LV010-10DP-M | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Space FPGA Configuration EEPROM |
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