- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19911 > AT17LV040-10TQU (Atmel)IC CONFIG SEEPROM 4M 3.3V 44TQFP PDF資料下載
參數(shù)資料
| 型號： | AT17LV040-10TQU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 25/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG SEEPROM 4M 3.3V 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 可編程類型： | 串行 EEPROM |
| 存儲容量： | 4Mb |
| 電源電壓： | 3 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 609 (CN2011-ZH PDF) |
| 配用： | ATDH2225-ND - CABLE ISP FOR AT17 ATDH2200E-ND - CONFIGURATOR PROGRAM BOARD KIT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁
8
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
4.10
A2
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
4.11
READY
Open collector reset state indicator. Driven Low during power-up reset, released when power-up
is complete. It is recommended to use a 4.7 k
pull-up resistor when this pin is used.
4.12
SER_EN
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to V
CC.
4.13
V
CC
3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.
5.
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The AT17LV Serial Configuration EEPROM has
been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil-
inx applications.
6.
Control of Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and
self-explanatory.
The DATA output of the AT17LV series configurator drives DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of the AT17LV series configurator.
The CEO output of any AT17LV series configurator drives the CE input of the next
configurator in a cascaded chain of EEPROMs.
SER_EN must be connected to V
CC (except during ISP).
The READY(1) pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
Note:
1. This pin is not available for the AT17LV65/128/256 devices.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-22M-CX | CONVERTER MOD DC/DC 10V 75W |
| VI-22H-CX | CONVERTER MOD DC/DC 52V 75W |
| LT4250LCS8 | IC CONTRLR HOTSWAP NEG 48V 8SOIC |
| ACB45DHRR | CONN CARD EXTEND 90POS .050" |
| VI-224-CX-F1 | CONVERTER MOD DC/DC 48V 75W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV040A-10BJC | 功能描述:IC SRL CONFG EEPROM 4M LV 44PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| AT17LV040A-10BJI | 功能描述:IC SRL CONFG EEPROM 4M LV 44PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| AT17LV040A-10CC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV040A-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV040A-10JC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。