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參數資料
| 型號： | AT17LV128-10BJC |
| 廠商： | Atmel Corp. |
| 元件分類： | FPGA |
| 英文描述： | FPGA Configuration EEPROM Memory |
| 中文描述： | FPGA配置EEPROM存儲器 |
| 文件頁數： | 21/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | AT17LV128-10BJC |
6
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
DATA
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
CLK
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WP1
WRITE PROTECT (1). Used to protect portions of memory during programming. Dis-
abled by default due to internal pull-down resistor. This input pin is not used during
FPGA loading operations. This pin is only available on AT17LV512/010/002 devices.
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
WP
Write protect (WP) input (when CE is Low) during programming only (SER_EN Low).
When WP is Low, the entire memory can be written. When WP is enabled (High), the
lowest block of the memory cannot be written. This pin is only available on
AT17LV65/128/256 devices.
WP2
WRITE PROTECT (2). Used to protect portions of memory during programming. Dis-
abled by default due to internal pull-down resistor. This input pin is not used during
FPGA loading operations. This pin is only available on AT17LV512/010 devices.
Pin Description
Name
I/O
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
AT17LV002
AT17LV040
8
DIP/
LAP/
SOIC
20
PLCC
20
SOIC
8
DIP/
LAP
20
PLCC
20
SOIC
8
DIP/
LAP/
SOIC
20
PLCC
20
SOIC
44
PLCC
44
TQFP
44
PLCC
44
TQFP
DATA
I/
O
1
221
211
212
40
2
40
CLK
I
2
442
432
435
43
5
43
WP1
I
–
–––
5––
–––
RESET/OE
I
3
663
683
68
19
13
19
13
WP2
I
–
7––
–––
CE
I
4
8
4
8
10
4
8
1021152115
GND
5
10
5
10
11
5
10
11
24
18
24
18
CEO
O
614
14
6
14
13
614
13
27
21
27
21
A2
I
–
READY
O
–
15
–
15
–
29232923
SER_EN
I
7
17
7
17
18
7
17
18
41
35
41
35
V
CC
8
2020
8
20
8
202044384438
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PDF描述 |
|---|---|
| AT17LV256-10BJC | PhotoMOS Relay; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Voltage:5V RoHS Compliant: No |
| AT17LV512-10BJC | FPGA Configuration EEPROM Memory |
| AT17LV65A-10BJC | FPGA Configuration EEPROM Memory |
| AT24C08SC-09BT | 1K X 8 I2C/2-WIRE SERIAL EEPROM, XMA8 |
| AT25080-10PC-1.8 | SPI Serial EEPROMs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AT17LV128-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV128-10CC | 功能描述:FPGA-配置存儲器 2M bit FPGA RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV128-10CI | 功能描述:FPGA-配置存儲器 3.3V 10MHz RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV128-10JC | 功能描述:FPGA-配置存儲器 CONFIG SERIAL EEPROM 128K 3.3V-10MHZ 10NS RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV128-10JI | 功能描述:FPGA-配置存儲器 1M-BIT CONFIG EEPROM 128K 3.3V - 10MHZ RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
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