參數(shù)資料
型號: AT17LV128-10JI
廠商: Atmel
文件頁數(shù): 23/26頁
文件大?。?/td> 0K
描述: IC EEPROM FPGA 128KB 20-PLCC
標準包裝: 50
可編程類型: 串行 EEPROM
存儲容量: 128kb
電源電壓: 3 V ~ 3.6 V,4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-LCC(J 形引線)
供應商設備封裝: 20-PLCC
包裝: 管件
產(chǎn)品目錄頁面: 609 (CN2011-ZH PDF)
配用: ATDH2225-ND - CABLE ISP FOR AT17
ATDH2200E-ND - CONFIGURATOR PROGRAM BOARD KIT
其它名稱: AT17LV12810JI
6
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
3.
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly
with the FPGA device control signals. All FPGA devices can control the entire configuration pro-
cess and retrieve data from the configuration EEPROM without requiring an external intelligent
controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA
output pin and enable the address counter. When RESET/OE is driven High, the configuration
EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the
output of the AT17LV series configurator. If CE is held High after the RESET/OE reset pulse, the
counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven Low,
the counter and the DATA output pin are enabled. When RESET/OE is driven High again, the
address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High,
this document will describe RESET/OE.
Note:
1. The CEO feature is not available on the AT17LV65 device.
4.
Pin Description
Name
I/O
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
AT17LV002
AT17LV040
8
DIP/
LAP/
SOIC
20
PLCC
20
SOIC
8
DIP/
LAP
20
PLCC
20
SOIC
8
DIP/
LAP/
SOIC
20
PLCC
20
SOIC
44
TQFP
44
TQFP
DATA
I/O
122121121
40
CLK
I
244243243
43
WP1
I
––––5––5––
RESET/OE
I
3
66368368
13
WP2
I
–7––7––
CE
I
4
8848
10
48
10
15
GND
5
10
10510
11510
11
18
CEO
O
614
14614
13
614
13
21
A2
I
READY
O
––––
15
––
15
23
SER_EN
I
7
17
17717
18717
18
35
V
CC
820
20820
20
38
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相關代理商/技術參數(shù)
參數(shù)描述
AT17LV128-10JI 09191 制造商:Atmel Corporation 功能描述:
AT17LV128-10NC 功能描述:FPGA-配置存儲器 CONFIG SERIAL EEPROM 128K 3.3V-10MHZ 10NS RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20
AT17LV128-10NI 功能描述:FPGA-配置存儲器 1M-BIT CONFIG EEPROM 128K 3.3V - 10MHZ RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20
AT17LV128-10PC 功能描述:FPGA-配置存儲器 1M-BIT CONFIG EEPROM 128K 3.3V - 10MHZ RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20
AT17LV128-10PI 功能描述:FPGA-配置存儲器 2M bit FPGA RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20