- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄352483 > AT17LV256A-10CC (Atmel Corp.) FPGA Configuration EEPROM Memory PDF資料下載
參數(shù)資料
| 型號： | AT17LV256A-10CC |
| 廠商： | Atmel Corp. |
| 元件分類： | FPGA |
| 英文描述： | FPGA Configuration EEPROM Memory |
| 中文描述： | FPGA配置EEPROM存儲器 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | AT17LV256A-10CC |
7
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN Low).
GND
Ground pin. A 0.2 F decoupling capacitor between V
CC and GND is recommended.
CEO
Chip Enable Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17LV series devices, the CEO pin of
one device must be connected to the CE input of the next device in the chain. It will stay
Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
A2
Device selection input, A2. This is used to enable (or select) the device during program-
ming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
READY
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. It is recommended to use a 4.7 k
pull-up resistor when this pin
is used.
SER_EN
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to V
CC.
V
CC
3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17LV256A-10CI | High-Speed CMOS Logic Dual 4-Input NAND Gates 14-SOIC -55 to 125 |
| AT17LV256A-10NC | FPGA Configuration EEPROM Memory |
| AT17LV256A-10NI | High-Speed CMOS Logic Dual 4-Input NAND Gates 14-SOIC -55 to 125 |
| AT17LV256A-10PC | FPGA Configuration EEPROM Memory |
| AT17LV256A-10PI | FPGA Configuration EEPROM Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV256A-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10JC | 功能描述:IC SRL CONFG EEPROM 256K 20-PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| AT17LV256A-10JI | 功能描述:IC SRL CONFG EEPROM 256K 20-PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| AT17LV256A-10NC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10NI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。