參數(shù)資料
型號(hào)： AT17LV256A-10JC
廠商： Atmel
文件頁(yè)數(shù)： 14/18頁(yè)
文件大?。?/td> 0K
描述： IC SRL CONFG EEPROM 256K 20-PLCC
標(biāo)準(zhǔn)包裝： 50
可編程類型： 串行 EEPROM
存儲(chǔ)容量： 256Kb
電源電壓： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
封裝/外殼： 20-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 20-PLCC
包裝： 管件
5
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
4.1
DATA
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
4.2
DCLK
Clock output or clock input. Rising edges on DCLK increment the internal address counter and
present the next bit of data to the DATA pin. The counter is incremented only if the RESET/OE
input is held High, the nCS input is held Low, and all configuration data has not been transferred
to the target device (otherwise, as the master device, the DCLK pin drives Low).
4.3
WP1
WRITE PROTECT (1). This pin is used to protect portions of memory during programming, and
it is disabled by default due to internal pull-down resistor. This input pin is not used during FPGA
loading operations. This pin is only available on AT17LV512A/010A/002A devices.
4.4
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low logic level
resets the address counter. A High logic level (with nCS Low) enables DATA and permits the
address counter to count. In the mode, if this pin is Low (reset), the internal oscillator becomes
inactive and DCLK drives Low. The logic polarity of this input is programmable and must be pro-
grammed active High (RESET active Low) by the user during programming for Altera
applications.
4.5
WP
Write protect (WP) input (when nCS is Low) during programming only (SER_EN Low). When
WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of
the memory cannot be written. This pin is only available on AT17LV65A/128A/256A devices.
4.6
nCS
Chip Select input (active Low). A Low input (with OE High) allows DCLK to increment the
address counter and enables DATA to drive out. If the AT17A series is reset with nCS Low, the
device initializes as the first (and master) device in a daisy-chain. If the AT17A series is reset
with nCS High, the device initializes as a subsequent AT17A series device in the chain.
4.7
GND
Ground pin. A 0.2 F decoupling capacitor between V
CC and GND is recommended.
4.8
nCASC
Cascade Select Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy-chain of AT17A series devices, the nCASC pin of one
device is usually connected to the nCS input pin of the next device in the chain, which permits
DCLK from the master configurator to clock data from a subsequent AT17A series device in the
chain. This feature is not available on the AT17LV65A device.
4.9
A2
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT17LV256A-10JI 功能描述:IC SRL CONFG EEPROM 256K 20-PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲(chǔ)容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件
AT17LV256A-10NC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
AT17LV256A-10NI 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
AT17LV256A-10PC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
AT17LV256A-10PI 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
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