- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19894 > AT17LV256A-10JI (Atmel)IC SRL CONFG EEPROM 256K 20-PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | AT17LV256A-10JI |
| 廠商： | Atmel |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 0K |
| 描述： | IC SRL CONFG EEPROM 256K 20-PLCC |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 可編程類型： | 串行 EEPROM |
| 存儲(chǔ)容量： | 256Kb |
| 電源電壓： | 3 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC |
| 包裝： | 管件 |
4
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
3.
Device Description
The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration EEPROM without requiring an external
controller.
The configuration EEPROM’s RESET/OE and nCS pins control the tri-state buffer on the DATA
output pin and enable the address counter and the oscillator. When RESET/OE is driven Low,
the configuration EEPROM resets its address counter and tri-states its DATA pin. The nCS pin
also controls the output of the AT17A series configurator. If nCS is held High after the
RESET/OE pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is
driven subsequently Low, the counter and the DATA output pin are enabled. When RESET/OE
is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regard-
less of the state of the nCS.
When the configurator has driven out all of its data and nCASC is driven Low, the device tri-
states the DATA pin to avoid contention with other configurators. Upon power-up, the address
counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High,
this document will describe RESET/OE.
4.
Pin Description
Note:
1. The nCASC feature is not available on the AT17LV65A device.
Name
I/O
AT17LV65A/
AT17LV128A/
AT17LV256A
AT17LV512A/
AT17LV010A
AT17LV002A
20
PLCC
8
PDIP
20
PLCC
32
TQFP
20
PLCC
32
TQFP
DATA
I/O
2
1
2
31
2
31
DCLK
I
42
4242
WP1
I
––
5454
RESET/OE
I
8
3
8787
nCS
I9
4
9
10
9
10
GND
10
5
10
12
10
12
nCASC
O
12
6
12151215
A2
I
READY
O
–
15
20
15
20
SER_EN
I
18
7
18
23
18
23
V
CC
20
8
20272027
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACB20DHBS | CONN EDGECARD 40POS R/A .050 DIP |
| LTC4211CMS | IC CONTROLLER HOT SWAP 10-MSOP |
| VI-21V-CY-F4 | CONVERTER MOD DC/DC 5.8V 50W |
| EYM08DRSD-S288 | CONN EDGECARD 16POS .156 EXTEND |
| RGM30DTMT | CONN EDGECARD 60POS R/A .156 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV256A-10NC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10NI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10PC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10PI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10SC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。