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參數(shù)資料
| 型號(hào)： | AT17LV256A-10SI |
| 廠商： | Atmel Corp. |
| 英文描述： | High Speed CMOS Logic Dual 4-Input AND Gates 14-PDIP -55 to 125 |
| 中文描述： | FPGA配置EEPROM存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 5/24頁(yè) |
| 文件大?。?/td> | 221K |
| 代理商： | AT17LV256A-10SI |
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13
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
AC Characteristics
V
CC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial
Symbol
Description
AT17LV65/128/256
AT17LV512/010/002/040
Units
Commercial
Industrial
Commercial
Industrial
MinMax
T
OE
OE to Data Delay
30
35
30
35
ns
TCE
CE to Data Delay
45
ns
T
CAC
CLK to Data Delay
50
55
50
ns
T
OH
Data Hold from CE, OE, or CLK
0
ns
TDF
CE or OE to Data Float Delay
50
ns
T
LC
CLK Low Time
20
ns
T
HC
CLK High Time
20
ns
T
SCE
CE Setup Time to CLK (to guarantee proper
counting)
35
40
20
25
ns
T
HCE
CE Hold Time from CLK (to guarantee proper
counting)
00
ns
T
HOE
OE High Time (guarantees counter is reset)
20
ns
F
MAX
Maximum Clock Frequency
12.5
15
MHz
AC Characteristics when Cascading
VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial
Symbol
Description
AT17LV65/128/256
AT17LV512/010/002/040
Units
Commercial
Industrial
Commercial
Industrial
MinMax
Min
Max
MinMax
T
CDF
CLK to Data Float Delay
50
ns
TOCK
CLK to CEO Delay
35
40
35
40
ns
T
OCE
CE to CEO Delay
35
ns
T
OOE
RESET/OE to CEO Delay
30
35
30
ns
FMAX
Maximum Clock Frequency
10
12.5
MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17LV256A-10TQC | High Speed CMOS Logic Dual 4-Input AND Gates 14-PDIP -55 to 125 |
| AT17LV256A-10TQI | High Speed CMOS Logic Dual 4-Input AND Gates 14-SOIC -55 to 125 |
| AT17LV512-10CC | High Speed CMOS Logic Dual 4-Input AND Gates 14-SOIC -55 to 125 |
| AT17LV512-10CI | High Speed CMOS Logic Dual 4-Input AND Gates 14-SOIC -55 to 125 |
| AT17LV512-10JC | High Speed CMOS Logic Dual 4-Input AND Gates 14-SOIC -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV256A-10TQC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10TQI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV512 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV512-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV512-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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