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參數(shù)資料
| 型號： | AT17LV65A-10CI |
| 廠商： | Atmel Corp. |
| 英文描述： | High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SOIC -55 to 125 |
| 中文描述： | FPGA配置EEPROM存儲器 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | AT17LV65A-10CI |
7
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN Low).
GND
Ground pin. A 0.2 F decoupling capacitor between V
CC and GND is recommended.
CEO
Chip Enable Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17LV series devices, the CEO pin of
one device must be connected to the CE input of the next device in the chain. It will stay
Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
A2
Device selection input, A2. This is used to enable (or select) the device during program-
ming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
READY
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. It is recommended to use a 4.7 k
pull-up resistor when this pin
is used.
SER_EN
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to V
CC.
V
CC
3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17LV65A-10NC | High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SOIC -55 to 125 |
| AT17LV65A-10NI | High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SOIC -55 to 125 |
| AT17LV65A-10PC | High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SOIC -55 to 125 |
| AT17LV65A-10PI | High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SO -55 to 125 |
| AT17LV65A-10SC | High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SO -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV65A-10JC | 功能描述:FPGA-配置存儲器 ASICS RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV65A-10JI | 功能描述:FPGA-配置存儲器 ASICS RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV65A-10NC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10NI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10PC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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